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INTEGRATED CIRCUITS
DATA SHEET
SAA7325 Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
Product specification File under Integrated Circuits, IC01 1999 Jun 17
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
CONTENTS 1 2 3 4 5 6 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.2 7.3 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.2 7.5.3 7.6 7.6.1 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.8 7.8.1 7.8.2 7.9 7.9.1 7.10 7.11 7.12 7.13 7.13.1 7.13.2 7.13.3 7.13.4 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Decoder part Principal operational modes of the decoder Decoding speed and crystal frequency Lock-to-disc mode Standby modes Crystal oscillator Data slicer and clock regenerator Demodulator Frame sync protection EFM demodulation Subcode data processing Q-channel processing EIAJ 3 and 4-wire subcode (CD graphics) interfaces V4 subcode interface FIFO and error corrector Flags output (CFLG) Audio functions De-emphasis and phase linearity Digital oversampling filter Concealment Mute, full-scale, attenuation and fade Peak detector DAC interface Internal bitstream digital-to-analog converter (DAC) External DAC interface EBU interface Format KILL circuit Audio features off The VIA interface Spindle motor control Motor output modes Spindle motor operating modes Loop characteristics FIFO overflow 7.14 7.14.1 7.14.2 7.14.3 7.14.4 7.14.5 7.14.6 7.14.7 7.14.8 7.14.9 7.14.10 7.14.11 7.15 7.15.1 7.15.2 7.15.3 7.15.4 7.15.5 7.15.6 7.15.7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18
SAA7325
Servo part Diode signal processing Signal conditioning Focus servo system Radial servo system Off-track counting Defect detection Off-track detection High-level features Driver interface Laser interface Radial shock detector Microcontroller interface Microcontroller interface (4-wire bus mode) Microcontroller interface (I2C-bus mode) Decoder registers and shadow registers Summary of functions controlled by decoder registers 0 to F Summary of functions controlled by shadow registers Summary of servo commands Summary of servo command parameters LIMITING VALUES CHARACTERISTICS OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING) OPERATING CHARACTERISTICS (I2S-BUS TIMING) OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING) APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1999 Jun 17
2
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
1
FEATURES
* Single speed operation * Integrated bitstream DAC with differential outputs, operating at 96fs with 3rd-order noise shaper; typical performance of -90 dB signal-to-noise ratio * Separate serial input and output interfaces allow data `loopback' mode for use of onboard DAC with external Electronic Shock Absorption (ESA) systems * Lock-to-disc mode * Full error correction strategy, t = 2 and e = 4 * Full CD graphics interface * All standard decoder functions implemented digitally on chip * FIFO overflow concealment for rotational shock resistance * Digital audio interface (EBU), audio and data * 2 and 4 times oversampling integrated digital filter, including fs mode * Audio data peak level detection * Kill interface for external DAC deactivation during digital silence * All SAA737x (CD7) digital servo and high-level functions * Low focus noise * Same playability performance as SAA737x (CD7) 3 ORDERING INFORMATION TYPE NUMBER SAA7325H
* Automatic closed-loop gain control available for focus and radial loops * Pulsed sledge support * Electronic damping of fast radial actuator during long jump * Microcontroller loading LOW * High-level servo control option * High-level mechanism monitor * Communication may be via I2C-bus or TDA1301/SAA7345 compatible bus * On-chip clock multiplier allows the use of 8.4672, 16.9344 or 33.8688 MHz crystals or ceramic resonators. 2 GENERAL DESCRIPTION
The SAA7325 (CD10) is a single chip combining the functions of a CD decoder, digital servo and bitstream DAC. The decoder/servo part is based on the SAA737x (CD7) and is software compatible with this design. Extra functions are controlled by use of `shadow' registers (see Section 7.15.3). Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application.
PACKAGE NAME QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm VERSION SOT393-1
1999 Jun 17
3
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
4 QUICK REFERENCE DATA SYMBOL VDD IDD fxtal Tamb Tstg S/NDAC PARAMETER supply voltage supply current crystal frequency ambient temperature storage temperature onboard DAC signal-to-noise ratio 1 kHz; 1fs; see Figs. 38 and 39 CONDITIONS - 8 -10 -55 -85 MIN. 3.0 TYP. 3.3 20 8.4672 - - -90 -
SAA7325
MAX. 3.6 35 +70 +125 -
UNIT V mA MHz C C dB
1999 Jun 17
4
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
5 BLOCK DIAGRAM
SAA7325
handbook, full pagewidth
D1 D2 8 9
D3 10
D4 11
VSSA1 4
VDDA2 VSSD2 VSSA2 VDDD1(P) VDDD2(C) VDDA1 VSSD1 VSSD3 14 5 17 33 50 58 52 57
R1 R2
12 13 ADC PREPROCESSING CONTROL FUNCTION OUTPUT STAGES 54 55 56 CONTROL PART RA FO SL
VRIN
7
Vref GENERATOR
SCL SDA RAB SILD
40 39 41 42 MICROCONTROLLER INTERFACE MOTOR CONTROL
64
LDON
59 60
MOTO1 MOTO2
HFIN HFREF ISLICE Iref
2 1 3 6 FRONT-END
DIGITAL PLL
SAA7325
ERROR CORRECTOR FLAGS 53 CFLG
EFM DEMODULATOR TEST1 TEST2 TEST3 25 31 44 SRAM 24 16 15 26 49 37 48 47 46 45 SUBCODE PROCESSOR PEAK DETECT BITSTREAM DAC VERSATILE PINS INTERFACE 20 21 18 43 DECODER MICROCONTROLLER INTERFACE 19 22 KILL 23 Vneg Vpos LN LP RN RP SERIAL DATA (LOOPBACK) INTERFACE 35 36 SCLI WCLI SDI TIMING RAM ADDRESSER SERIAL DATA INTERFACE EBU INTERFACE TEST 51 DOBM AUDIO PROCESSOR
30 29 28 27
SELPLL CRIN CROUT CL16 CL11/4
EF SCLK WCLK DATA
SBSY SFSY SUB RCK
STATUS
RESET
38 63 V1 34 V2/V3 61 V4 62 V5 32
MGL681
KILL
Fig.1 Block diagram.
1999 Jun 17
5
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
6 PINNING SYMBOL HFREF HFIN ISLICE VSSA1 VDDA1 Iref VRIN D1 D2 D3 D4 R1 R2 VSSA2 CROUT CRIN VDDA2 LN LP Vneg Vpos RN RP SELPLL TEST1 CL16 DATA WCLK SCLK EF TEST2 KILL VSSD1 V2/V3 WCLI SDI SCLI RESET SDA SCL 1999 Jun 17 PIN 1 2 3 4(1) 5(1) 6 7 8 9 10 11 12 13 14(1) 15 16 17(1) 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33(1) 34 35 36 37 38 39 40 comparator common mode input comparator signal input current feedback output from data slicer analog ground 1 analog supply voltage 1 reference current output pin reference voltage for servo ADCs unipolar current input 1 (central diode signal input) unipolar current input 2 (central diode signal input) unipolar current input 3 (central diode signal input) unipolar current input 4 (central diode signal input) unipolar current input 1 (satellite diode signal input) unipolar current input 2 (satellite diode signal input) analog ground 2 crystal/resonator output crystal/resonator input analog supply voltage 2 DAC left channel differential negative output DAC left channel differential positive output DAC negative reference input DAC positive reference input DAC right channel differential negative output DAC right channel differential positive output selects whether internal clock multiplier PLL is used test control input 1 (this pin should be tied LOW) 16.9344 MHz system clock output serial d4(1) data output (3-state) word clock output (3-state) serial bit clock output (3-state) C2 error flag output (3-state) test control input 2 (this pin should be tied LOW) kill output (programmable; open-drain) digital ground 1 versatile I/O: versatile input 2 or versatile output 3 (open-drain) word clock input (for data loopback to DAC) serial data input (for data loopback to DAC) serial bit clock input (for data loopback to DAC) power-on reset input (active LOW) microcontroller interface data I/O line (open-drain output) microcontroller interface clock line input 6 DESCRIPTION
SAA7325
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SYMBOL RAB SILD STATUS TEST3 RCK SUB SFSY SBSY CL11/4 VSSD2 DOBM VDDD1(P) CFLG RA FO SL VDDD2(C) VSSD3 MOTO1 MOTO2 V4 V5 V1 LDON Note 1. All supply pins must be connected to the same external power supply voltage. PIN 41 42 43 44 45 46 47 48 49 50(1) 51 52(1) 53 54 55 56 57(1) 58(1) 59 60 61 62 63 64 DESCRIPTION
SAA7325
microcontroller interface R/W and load control line input (4-wire bus mode) microcontroller interface R/W and load control line input (4-wire bus mode) servo interrupt request line/decoder status register output (open-drain) test control input 3 (this pin should be tied LOW) subcode clock input P-to-W subcode bits output (3-state) subcode frame sync output (3-state) subcode block sync output (3-state) 11.2896 or 4.2336 MHz (for microcontroller) clock output digital ground 2 bi-phase mark output (externally buffered; 3-state) digital supply voltage 1 for periphery correction flag output (open-drain) radial actuator output focus actuator output sledge control output digital supply voltage 2 for core digital ground 3 motor output 1; versatile (3-state) motor output 2; versatile (3-state) versatile output 4 versatile output 5 versatile input 1 laser drive on output (open-drain)
1999 Jun 17
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Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
57 VDDD2(C)
handbook, full pagewidth
52 VDDD1(P)
60 MOTO2
59 MOTO1
58 VSSD3
50 VSSD2
HFREF 1 HFIN 2 ISLICE 3 VSSA1 4 VDDA1 5 Iref 6 VRIN 7 D1 8
49 CL11/4
51 DOBM
64 LDON
53 CFLG
54 RA
55 FO
63 V1
62 V5
61 V4
56 SL
48 SBSY 47 SFSY 46 SUB 45 RCK 44 TEST3 43 STATUS 42 SILD 41 RAB
SAA7325H
D2 9 D3 10 D4 11 R1 12 R2 13 VSSA2 14 CROUT 15 CRIN 16 Vneg 20 Vpos 21 RN 22 RP 23 SELPLL 24 TEST1 25 CL16 26 DATA 27 WCLK 28 SCLK 29 EF 30 TEST2 31 VDDA2 17 KILL 32 LN 18 LP 19 40 SCL 39 SDA 38 RESET 37 SCLI 36 SDI 35 WCLI 34 V2/V3 33 VSSD1
MGL693
Fig.2 Pin configuration.
7 7.1
FUNCTIONAL DESCRIPTION Decoder part PRINCIPAL OPERATIONAL MODES OF THE DECODER
7.1.1
(see Section 7.2). The range of crystal and oscillator frequencies possible is controlled via decoder register B and shown in Table 1. The MSB of decoder register B must be set to logic 0. The internal clock multiplier is controlled by SELPLL, and should only be used if a 8.4672 or 16.9344 MHz crystal, ceramic resonator or external clock is present.
The decoding part supports a full audio specification at single-speed (n = 1). A simplified data flow through the decoder part is illustrated in Fig.7. 7.1.2 DECODING SPEED AND CRYSTAL FREQUENCY
The SAA7325 is a single-speed decoding device, with an internal Phase-Locked Loop (PLL) clock multiplier allowing a choice of different crystals and oscillators to be used 1999 Jun 17 8
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.1.3 LOCK-TO-DISC MODE
SAA7325
Although nominally a single-speed device, for electronic shock absorption applications the SAA7325 can be put into lock-to-disc mode. This allows Constant Angular Velocity (CAV) disc playback with varying input data rates from the inside-to-outside of the disc. In the lock-to-disc mode, the FIFO is blocked and the decoder will adjust its output data rate to the disc speed. Hence, the frequency of the I2S-bus (WCLK and SCLK) clocks are dependent on the disc speed. In the lock-to-disc mode there is a limit on the maximum variation in disc speed that the SAA7325 will follow. Disc speeds must always be within 25% to 100% range of their nominal value. The lock-to-disc mode is enabled/disabled by decoder register E. 7.1.4 STANDBY MODES
* Standby 1: `CD-STOP' mode; most I/O functions are switched off * Standby 2: `CD-PAUSE' mode; audio output features are switched off, but the motor loop, the motor output and the subcode interfaces remain active; this is also called a `Hot Pause'. In the standby modes the various pins will have the following values: * MOTO1 and MOTO2: put in high-impedance, PWM mode (standby 1 and reset: operating in standby 2); put in high-impedance, PDM mode (standby 1 and reset: operating in standby 2) * SCL and SDA: no interaction; normal operation continues * SCLK, WCLK, DATA, EF and DOBM: 3-state in both standby modes; normal operation continues after reset * CRIN, CROUT, CL16 and CL11/4: no interaction; normal operation continues * V1, V2/V3, V4, V5 and CFLG: no interaction; normal operation continues.
The SAA7325 may be placed in two standby modes selected by decoder register B (it should be noted that the device core is still active):
Table 1
Operating frequencies CRYSTAL FREQUENCY (MHz) SELPLL 33.8688 00XX 00XX 01XX 01XX 0 1 0 1 - - - 16.9344 - - 8.4672 - - - 11.2896 11.2896 5.6448 11.2896 CL11 FREQUENCY (MHz)(2)
REGISTER B(1)
Notes 1. The MSB of register B must be held at 0 (i.e. 0XXX). 2. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used and SELPLL = 0. CL11 is available on the CL11/4 output, enabled by programming shadow register 3 (see Section 7.15.3).
1999 Jun 17
9
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.2 Crystal oscillator 7.3
SAA7325
Data slicer and clock regenerator
The crystal oscillator is a conventional 2-pin design operating between 8 and 35 MHz. This oscillator is capable of operating with ceramic resonators and with both fundamental and third overtone crystals. External components should be used to suppress the fundamental output of the third overtone crystals as shown in Figs 3 and 4. Typical oscillation frequencies required are 8.4672, 16.9344 or 33.8688 MHz depending on the internal clock settings used and whether or not the clock multiplier is enabled (see Table 1).
The SAA7325 has an integrated slice level comparator which can be clocked by the crystal frequency clock, or 4 times the crystal frequency clock (if SELPLL is set HIGH while using a 16.9344 MHz crystal and register 4 is set to 0XXX), or 8 times the crystal frequency clock (if SELPLL is set HIGH while using an 8.4672 MHz crystal, and register 4 is set to 0XXX). The slice level is controlled by an internal current source applied to an external capacitor under the control of the Digital Phase-Locked Loop (DPLL). Regeneration of the bit clock is achieved with an internal fully digital PLL. No external components are required and the bit clock is not output. The PLL has two registers (8 and 9) for selecting bandwidth and equalization. The PLL response is shown in Fig.5.
handbook, halfpage
SAA7325
OSCILLATOR
CROUT
8.4672 MHz
CRIN
For certain applications an off-track input is necessary. This is internally connected from the servo part (its polarity can be changed by the foc_parm1 parameter), but may be input via the V1 pin if selected by register C. If this flag is HIGH, the SAA7325 will assume that its servo part is following on the wrong track, and will flag all incoming HF data as incorrect.
33 pF
33 pF
MGL694
handbook, halfpage
Fig.3 8.4672 MHz fundamental configuration.
PLL loop response
3. PLL, LPF
handbook, halfpage
f 2. PLL bandwidth OSCILLATOR 1. PLL integrator
MGS178
SAA7325
CROUT
33.8688 MHz
CRIN
1, 2 and 3 are all programmable via decoder register 8.
3.3 H
Fig.5 Digital PLL loop response.
10 pF
MGL695
10 pF
1 nF
Fig.4 33.8688 MHz overtone configuration.
1999 Jun 17
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Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
crystal clock 100 nF VSSA 1 nF HF input 2.2 k 22 k HFIN DPLL 47 pF HFREF D Q
100 A VSS
MGS179
100 nF VSSA
ISLICE 100 A
VDD
Fig.6 Data slicer showing typical application components.
7.4 7.4.1
Demodulator FRAME SYNC PROTECTION
A double timing system is used to protect the demodulator from erroneous sync patterns in the serial data. The master counter is only reset if: * A sync coincidence is detected; sync pattern occurs 588 1 EFM clocks after the previous sync pattern * A new sync pattern is detected within 6 EFM clocks of its expected position. The sync coincidence signal is also used to generate the PLL lock signal, which is active HIGH after 1 sync coincidence found, and reset LOW if during 61 consecutive frames no sync coincidence is found. The PLL lock signal can be accessed via the SDA or STATUS pins selected by decoder registers 2 and 7.
Also incorporated in the demodulator is a Run Length 2 (RL2) correction circuit. Every symbol detected as RL2 will be pushed back to RL3. To do this, the phase error of both edges of the RL2 symbol are compared and the correction is executed at the side with the highest error probability. 7.4.2 EFM DEMODULATION
The 14-bit EFM data and subcode words are decoded into 8-bit symbols.
1999 Jun 17
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1999 Jun 17
1 0 V4 RCK 0: reg D = XX01 CD GRAPHICS INTERFACE V4 SUBCODE INTERFACE reg F SUBCODE PROCESSOR output from data slicer DIGITAL PLL AND DEMODULATOR 1: decoder reg A = XX0X 0: decoder reg A XX1X 1 0 FIFO
Philips Semiconductors
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SBSY SFSY SUB MICROCONTROLLER INTERFACE SDA
EBU INTERFACE
DOBM
decoder reg A
1: shadow reg 7 = XX1X 0: shadow reg 7 = XX0X SCLK WCLK DATA EF
1 1: decoder reg 3 = XX10 (1fs mode) 0: decoder reg 3 XX10 0 1: no pre-emphasis detected OR reg D = 01XX (de-emphasis signal at V5) 0: pre-emphasis detected AND reg D 01XX
12
ONBOARD DAC
1 0
1 ERROR CORRECTOR FADE/MUTE/ INTERPOLATE DIGITAL FILTER 0
PHASE COMPENSATION
1 0 1 0 1 0 I2S/EIAJ BUS INTERFACE 1 0
LN LP RN RP
Vneg 1: shadow reg 7 = XXX1 0: shadow reg 7 = XXX0
decoder reg 3 KILL V3
DE-EMPHASIS FILTER decoder reg 3 1: decoder reg 3 101X 0: decoder reg 3 = 101X (CD-ROM modes)
KILL
1: shadow reg 7 = XX1X 0: shadow reg 7 = XX0X I2S/EIAJ LOOPBACK INTERFACE WCLI SCLI SDI
decoder reg C
MGS180
Product specification
SAA7325
Fig.7 Simplified data flow of decoder functions.
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.5 7.5.1 Subcode data processing Q-CHANNEL PROCESSING 7.5.3 V4 SUBCODE INTERFACE
SAA7325
The 96-bit Q-channel word is accumulated in an internal buffer. The last 16 bits are used internally to perform a Cyclic Redundancy Check (CRC). If the data is good, the SUBQREADY-I signal will go LOW. SUBQREADY-I can be read via the SDA or STATUS pins, selected via decoder register 2. Good Q-channel data may be read from SDA. 7.5.2 EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)
INTERFACES
Data of subcode channels, Q-to-W, may be read via pin V4 if selected via decoder register D. The format is similar to RS232 and is illustrated in Fig.9. The subcode sync word is formed by a pause of 200 s minimum. Each subcode byte starts with a logic 1 followed by 7 bits (Q-to-W). The gap between bytes is variable between 11.3 and 90 s. The subcode data is also available in the EBU output (DOBM) in a similar format.
Data from all the subcode channels (P-to-W) may be read via the subcode interface, which conforms to EIAJ CP-2401. The interface is enabled and configured as either a 3 or 4-wire interface via decoder register F. The subcode interface output formats are illustrated in Fig.8, where the RCK signal is supplied by another device such as a CD graphics decoder.
handbook, full pagewidth
SF0
SF1
SF2
SF3
SF97
SF0
SF1
SBSY SFSY RCK P-W SUB EIAJ 4-wire subcode interface P-W P-W
SF0 SFSY RCK
SF1
SF2
SF3
SF97
SF0
SF1
P-W SUB
P-W
P-W
EIAJ 3-wire subcode interface
SFSY RCK P SUB Q R S T U V W
MBG410
Fig.8 EIAJ subcode (CD graphics) interface format.
1999 Jun 17
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Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
200 s min W96 1
11.3 s Q R S T U V W
11.3 s min 90 s max 1 Q
MGL719
n = disc speed.
Fig.9 Subcode format and timing on pin V4.
7.6
FIFO and error corrector
7.6.1
FLAGS OUTPUT (CFLG)
The SAA7325 has a 8 frame FIFO. The error corrector is a t = 2, e = 4 type, with error corrections on both C1 (32 symbol) and C2 (28 symbol) frames. Four symbols are used from each frame as parity symbols. This error corrector can correct up to two errors on the C1 level and up to four errors on the C2 level. The error corrector also contains a flag processor. Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. C1 generates output flags which are read after (de-interleaving) by C2, to help in the generation of C2 output flags. The C2 output flags are used by the interpolator for concealment of uncorrectable errors. They are also output via the EBU signal (DOBM). The EF output will flag bytes in error in both audio and CD-ROM modes.
The flags output pin CFLG shows the status of the error corrector and interpolator and is updated every frame (7.35 x n kHz). In the SAA7325 chip a 1-bit flag is present on the CFLG pin as illustrated in Fig.10. This signal shows the status of the error corrector and interpolator. The first flag bit, F1, is the absolute time sync signal, the FIFO-passed subcode sync and relates the position of the subcode sync to the audio data (DAC output). This flag may also be used in a super FIFO or in the synchronization of different players. The output flags can be made available at bit 4 of the EBU data format (LSB of the 24-bit data word), if selected by decoder register A.
handbook, full pagewidth
33.9 s F8
11.3 s F1 F2 F3 F4 F5 F6 F7 F8
33.9 s F1
MGL720
n = disc speed.
Fig.10 Flag output timing diagram.
1999 Jun 17
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Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
Table 2 F1 0 1 X X X X X X X X X X X X X X 7.7 7.7.1 Output flags F2 X X 0 0 1 1 X X X X X X X X X X F3 X X 0 1 0 1 X X X X X X X X X X F4 X X X X X X 0 0 0 0 1 1 X X X X F5 X X X X X X 0 0 1 1 0 1 X X X X F6 X X X X X X X X X X X X 0 0 1 1 F7 X X X X X X X X X X X X 0 1 0 1 F8 X X X X X X 0 1 0 1 0 1 X X X X no absolute time sync absolute time sync C1 frame contained no errors C1 frame contained 1 error C1 frame contained 2 errors C1 frame uncorrectable C2 frame contained no errors C2 frame contained 1 error C2 frame contained 2 errors C2 frame contained 3 errors C2 frame contained 4 errors C2 frame uncorrectable no interpolations at least one 1-sample interpolation at least one hold and no interpolations DESCRIPTION
SAA7325
at least one hold and one 1-sample interpolation Table 3 Filter specification STOP BAND - - 24 kHz 24 to 27 kHz 27 to 35 kHz 35 to 64 kHz 64 to 68 kHz 68 kHz 69 to 88 kHz ATTENUATION 0.001 dB 0.03 dB 25 dB 38 dB 40 dB 50 dB 31 dB 35 dB 40 dB
Audio functions DE-EMPHASIS AND PHASE LINEARITY
PASS BAND 0 to 9 kHz 19 to 20 kHz - - - - - - - 7.7.3
When pre-emphasis is detected in the Q-channel subcode, the digital filter automatically includes a de-emphasis filter section. When de-emphasis is not required, a phase compensation filter section controls the phase of the digital oversampling filter to 1 within the band 0 to 16 kHz. With de-emphasis the filter is not phase linear. If the de-emphasis signal is set to be available at V5, selected via decoder register D, then the de-emphasis filter is bypassed. 7.7.2 DIGITAL OVERSAMPLING FILTER
CONCEALMENT
For optimizing performance with an external DAC, the SAA7325 contains a 2 to 4 times oversampling IIR filter. The filter specification of the 4 times oversampling filter is given in Table 3. These attenuations do not include the sample-and-hold at the external DAC output or the DAC post filter. When using the oversampling filter, the output level is scaled -0.5 dB down to avoid overflow on full-scale sine wave inputs (0 to 20 kHz).
A 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. The erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels have independent interpolators. If more than one consecutive non-correctable sample is found, the last good sample is held. A 1-sample linear interpolation is then performed before the next good sample (see Fig.11). In CD-ROM modes (i.e. the external DAC interface is selected to be in a CD-ROM format) concealment is not executed.
1999 Jun 17
15
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.7.4 MUTE, FULL-SCALE, ATTENUATION AND FADE 7.7.5 PEAK DETECTOR
SAA7325
A digital level controller is present on the SAA7325 which performs the functions of soft mute, full-scale, attenuation and fade; these are selected via decoder register 0: * Mute: signal reduced to 0 in a maximum of 128 steps; 3 ms * Attenuate: signal scaled by -12 dB * Full-scale: ramp signal back to 0 dB level; from mute takes 3 ms * Fade: activates a 128 stage counter which allows the signal to be scaled up/down by 0.07 dB steps - 128 = full-scale - 120 = -0.5 dB (i.e. full-scale if oversampling filter used) - 32 = -12 dB - 0 = mute.
The peak detector measures the highest audio level (absolute value) on positive peaks for left and right channels. The 8 most significant bits are output in the Q-channel data in place of the CRC bits. Bits 81 to 88 contain the left peak value (bit 88 = MSB) and bits 89 to 96 contain the right peak value (bit 96 = MSB). The values are reset after reading Q-channel data via SDA.
Interpolation
Hold
Interpolation
OK
Error
OK
Error
Error
Error
OK
OK
MGA372
Fig.11 Concealment mechanism.
1999 Jun 17
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Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.8 7.8.1 DAC interface INTERNAL BITSTREAM DIGITAL-TO-ANALOG CONVERTER (DAC)
SAA7325
The onboard bitstream DAC operates at a clock frequency of 96fs and is designed for operation with an audio input at 1fs. Optimum performance is dependent on the application circuit used and careful consideration should be given to the recommended application circuits shown in Figs. 38 and 39. The onboard DAC is controlled from shadow register 7 (see Section 7.15.3 for definition of shadow registers). This shadow register controls routing of data into the onboard DAC and also controls the DAC output pins, which can be held at zero when the onboard DAC is not required; see Table 4. Table 4 Shadow register SHADOW ADDRESS 0111 (7H) REGISTER control of onboard DAC DATA XXX0 XXX1 XX0X XX1X FUNCTION hold onboard DAC outputs at zero enable onboard DAC outputs use external DAC or route audio data into onboard DAC (loopback mode) route audio data into onboard DAC (non-loopback mode) RESET reset - reset -
SHADEN 1
Audio data from the decoder part of SAA7325 can be routed as described in the following two subsections:
7.8.1.1
Use onboard DAC
In this mode, shadow register 7 should be set to XX11. This routes audio data from the decoder part of CD10 into the onboard DAC and enables the DAC output pins (LN, LP, RN and RP). It should be noted that the DAC interface format (set by decoder register 3) must be set to 16-bit 1fs mode, either I2S-bus or EIAJ format, for optimum DAC performance to be achieved. CD-ROM mode can also be used if interpolation is not required. When using this mode, the serial data output pins for interfacing with an external DAC (SCLK, WCLK, DATA and EF) are set to high-impedance.
The serial data from an external ESA IC can then also be input to the onboard DAC on the SAA7325 by utilising the serial data input interface (SCLI, SDI and WCLI). In this mode, a wide range of data formats to the external ESA IC can be programmed as shown in Table 5. However, the serial input on the SAA7325 will always expect the input data from the ESA IC to be 16 bit 1fs and the same data format, either I2S-bus or EIAJ, as the serial output format (set by decoder register 3).
7.8.1.2
Loopback external data into onboard DAC
The onboard DAC can also be set to accept serial data inputs from an external source, e.g. an Electronic Shock Absorption (ESA) IC. This is known as loopback mode and is enabled by setting shadow register 7 to XX01. This enables the serial data output pins (SCLK, WCLK, DATA and EF) so that data can be routed from the SAA7325 to an external ESA system (or external DAC).
1999 Jun 17
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Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.8.2 EXTERNAL DAC INTERFACE
SAA7325
Audio data from the SAA7325 decoder can be sent to an external DAC, identical to the SAA737x series. This is similar to the `loopback' mode, but in this case the internal DAC outputs can be held at zero. i.e. shadow register 7 is set to XX00. The SAA7325 is compatible with a wide range of external DACs. Eleven formats are supported and are given in Table 5. Figures 12 and 13 show the Philips I2S-bus and the EIAJ data formats respectively. When the decoder is operated in lock-to-disc mode, the SCLK frequency is dependent on the disc speed factor `d'. Table 5 DAC interface formats SAMPLE FREQUENCY fs fs fs fs fs 4fs 4fs 4fs 2fs 2fs 2fs NUMBER OF BITS 16 16 16/18(1) 16 18 16 18 18 16 18 18
All formats are MSB first and fs is (44.1 x n) kHz. The polarity of the WCLK and the data can be inverted; selectable by decoder register 7. It should be noted that EF is only a defined output in CD-ROM and 1fs modes. When using an external DAC (or when using the onboard DAC in non-loopback mode), the serial data inputs to the onboard DAC (SCLI, SDI and WCLI) should be left unconnected.
REGISTER 3 1010 1011 1110 0010 0110 0000 0100 1100 0011 0111 1111 Note
SCLK (MHz) 2.1168 2.1168 2.1168 2.1168 2.1168 8.4672 8.4672 8.4672 4.2336 4.2336 4.2336
FORMAT CD-ROM (I2S-bus) CD-ROM (EIAJ) Philips I2S-bus 16/18 bits(1) EIAJ 16 bits EIAJ 18 bits EIAJ 16 bits EIAJ 18 bits Philips I2S-bus 18 bits EIAJ 16 bits EIAJ 18 bits Philips I2S-bus 18 bits
INTERPOLATION no no yes yes yes yes yes yes yes yes yes
1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated then the first 18 bits contain data.
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SCLK DATA 1 0 15 14 1 0 15 14 LEFT CHANNEL DATA (WCLK NORMAL POLARITY) WCLK EF LSB error flag (CD-ROM AND Ifs MODES ONLY) MSB error flag LSB error flag MSB error flag
MBG424
Philips Semiconductors
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
Fig.12 Philips I2S-bus data format (16-bit word length shown). 19
SCLK DATA 0 17 LEFT CHANNEL DATA WCLK
EF (CD-ROM AND Ifs MODES ONLY)
0
17
MSB error flag
LSB error flag
MSB error flag
Product specification
MBG423
SAA7325
Fig.13 EIAJ data format (18-bit word length shown).
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.9 EBU interface 7.9.1 FORMAT
SAA7325
The bi-phase mark digital output signal at pin DOBM is in accordance with the format defined by the IEC958 specification. Three different modes can be selected via decoder register A: * DOBM pin held LOW * Data taken before concealment, mute and fade (must always be used for CD-ROM modes) * Data taken after concealment, mute and fade. Table 6 Format BITS 0 to 3 4 to 7 4 8 to 27 28 29 30 31 Description of table 6 - not used; normally zero
The digital audio output consists of 32-bit words (`subframes') transmitted in bi-phase mark code (two transitions for a logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384. The formats are given in Table 6.
FUNCTION Sync Auxiliary Error flags Audio sample Validity flag User data Channel status Parity bit Table 7
DESCRIPTION
CFLG error and interpolation flags when selected by register A first 4 bits not used (always zero) twos complement LSB = bit 12, MSB = bit 27 valid = logic 0 used for subcode data (Q-to-W) control bits and category code even parity for bits 4 to 30
FUNCTION Sync
DESCRIPTION The sync word is formed by violation of the bi-phase rule and therefore does not contain any data. Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations: sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample (no block start) and sync W: word contains right sample. Left and right samples are transmitted alternately. Audio samples are flagged (bit 28 = 1) if an error has been detected but was uncorrectable. This flag remains the same even if data is taken after concealment. Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is asynchronous with the block rate. The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192 channel status bits. The category code is always CD. The bit assignment is given in Table 8.
Audio sample Validity flag User data Channel status
Table 8
Bit assignment BITS 0 to 3 4 to 7 8 to 15 28 to 29 6 to 27 and 30 to 191 DESCRIPTION copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when copy permitted; bit 3 is logic 1 when recording has pre-emphasis always zero CD: bit 8 = logic 1, all other bits = logic 0 set by register A; 10 = level I; 00 = level II; 01 = level III always zero
FUNCTION Control Reserved mode Category code Clock accuracy Remaining
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.10 KILL circuit
SAA7325
The KILL circuit detects digital silence by testing for an all-zero or all-ones data word in the left or right channel prior to the digital filter. The output is switched to active LOW when silence has been detected for at least 270 ms, or if mute is active, or in CD-ROM modes. Two modes are available which can be selected by decoder register C: * Pin KILL: KILL active LOW indicates silence detected on both left and right channels * Pin KILL: KILL active LOW indicates silence detected on left channel. V3 active LOW indicates silence detected on right channel. It should be noted that when mute is active or in CD-ROM modes the output(s) are switched LOW. 7.11 Audio features off
It should be noted that the EBU output should be set LOW prior to switching the audio features off and after switching audio features back on a full-scale command should be given. 7.12 The VIA interface
The SAA7325 has four pins that can be reconfigured for different applications. One of these pins, V2/V3, can be programmed as an input (V2) or as an output (V3). Control of the V2/V3 pin is via shadow register 3; see Table 9: Selection of the V2/V3 pin does not affect the function programmed by decoder register C i.e. the V2/V3 pin can be changed from V2 to V3 function either before or after setting the desired function via decoder register 1100. Selection of, for instance, a V3 function while the V2/V3 pin is set to V2 will not affect the V2 functionality. The functions of these versatile pins is identical to the SAA737x series. The functions of these versatile pins is programmed by decoder registers C and D, as shown in Table 10.
The audio features can be turned off (selected by decoder register E) which affects the following functions: * Digital filter, fade, peak detector, KILL circuit (but outputs KILL, V3 still active) are disabled * V5 (if selected to be the de-emphasis flag output) and the EBU outputs become undefined. Table 9 V2/V3 configuration ADDRESS 0011 (3H) REGISTER control of V2/V3 pin DATA 0XXX 1XXX
SHADEN 1
FUNCTION V2/V3 pin configured as V2 input V2/V3 pin configured as V3 output (open-drain) -
RESET reset
Table 10 Pin applications PIN NAME V1 PIN NUMBER 63 TYPE input REGISTER REGISTER ADDRESS DATA 1100 - - 1100 - - 1101 - - - 1101 - - XXX1 XXX0 - XX0X X01X X11X 0000 XX01 XX10 XX11 01XX 10XX 11XX 21 FUNCTION external off-track signal input internal off-track signal used; input may be read via decoder status bit; selected via register 2 input may be read via decoder status bit; selected via register 2 KILL output for right channel output = 0 output = 1 4-line motor drive (using V4 and V5) Q-to-W subcode output output = 0 output = 1 de-emphasis output (active HIGH) output = 0 output = 1
V2 V3
36 36
input output
V4
61
output
V5
62
output
1999 Jun 17
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.13 7.13.1 Spindle motor control MOTOR OUTPUT MODES
SAA7325
Pulse density output mode
7.13.1.1
The spindle motor speed is controlled by a fully integrated digital servo. Address information from the internal 8 frame FIFO and disc speed information are used to calculate the motor control output signals. Several output modes, selected by decoder register 6, are supported: * Pulse density, 2-line (true complement output), 1 MHz sample frequency * PWM output, 2-line, 22.05 kHz modulation frequency * PWM output, 4-line, 22.05 kHz modulation frequency * CDV motor mode.
In the pulse density mode the motor output pin (MOTO1) is the pulse density modulated motor output signal. A 50% duty factor corresponds with the motor not actuated, higher duty factors mean acceleration, lower mean braking. In this mode, the MOTO2 signal is the inverse of the MOTO1 signal. Both signals change state only on the edges of a (1 x n) MHz internal clock signal. Possible application diagrams are illustrated in Fig.14.
7.13.1.2
PWM output mode (2-line)
In the PWM mode the motor acceleration signal is put in pulse-width modulation form on the MOTO1 output. The motor braking signal is pulse-width modulated on the MOTO2 output. The timing is illustrated in Fig.15. A typical application diagram is illustrated in Fig.16.
22 k MOTO1 10 nF VSS
22 k
+ -
M
+ -
VSS
MOTO2 10 nF
VDD 22 k
22 k MOTO1 22 k VSS 10 nF VSS
+ -
22 k 22 k
M
VSS
VDD
MGA363 - 1
Fig.14 Motor pulse density application diagrams.
t rep = 45 s MOTO1 MOTO2
t dead
240 ns
Accelerate
Brake
MGA366
Fig.15 2-line PWM mode timing.
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Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
+
M 10 100 nF
MOTO1
MOTO2
VSS
MGA365 - 2
Fig.16 Motor 2-line PWM mode application diagram.
7.13.1.3
PWM output mode (4-line)
Using two extra outputs from the versatile pins interface, it is possible to use the SAA7325 with a 4-input motor bridge. The timing is illustrated in Fig.17. A typical application diagram is illustrated in Fig.18.
t rep = 45 s MOTO1 MOTO2 V4 V5
t dead
240 ns
t ovl = 240 ns
MGA367 - 1
Accelerate
Brake
Fig.17 4-line PWM mode timing.
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Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
+
V4
V5
M 10 100 nF
MOTO1
MOTO2
VSS
MGA364 - 2
Fig.18 Motor 4-line PWM mode application diagram.
7.13.1.4
CDV/CAV output mode
7.13.2.1
Power limit
In the CDV motor mode, the FIFO position will be put in pulse-width modulated form on the MOTO1 pin [carrier frequency (300 x d) Hz], where `d' is the disc speed factor. The PLL frequency signal will be put in pulse-density modulated form (carrier frequency 4.23 MHz) on the MOTO2 pin. The integrated motor servo is disabled in this mode. The PWM signal on MOTO1 corresponds to a total memory space of 20 frames, therefore the nominal FIFO position (half full) will result in a PWM output of 60%. In the lock to-disc (CAV) mode the CDV motor mode is the only mode that can be used to control the motor. 7.13.2 SPINDLE MOTOR OPERATING MODES
In start mode 1, start mode 2, stop mode 1 and stop mode 2, a fixed positive or negative voltage is applied to the motor. This voltage can be programmed as a percentage of the maximum possible voltage, via register 6, to limit current drain during start and stop. The following power limits are possible: * 100% (no power limit), 75%, 50%, or 37% of maximum. 7.13.3 LOOP CHARACTERISTICS
The gain and crossover frequencies of the motor control loop can be programmed via decoder registers 4 and 5. The following parameter values are possible: * Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32 * Crossover frequency f4: 0.5 Hz, 0.7 Hz, 1.4 Hz and 2.8 Hz * Crossover frequency f3: 0.85 Hz, 1.71 Hz and 3.42 Hz.
The operation modes of the motor servo is controlled by decoder register 1 (see Table 11). In the SAA7325 decoder there is an anti-windup mode for the motor servo, selected via decoder register 1. When the anti-windup mode is activated the motor servo integrator will hold if the motor output saturates.
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.13.4 FIFO OVERFLOW
SAA7325
If FIFO overflow occurs during Play mode (e.g.: as a result of motor rotational shock), the FIFO will be automatically reset to 50% and the audio interpolator tries to conceal as much as possible to minimize the effect of data loss. Table 11 Operating modes MODE Start mode 1 Start mode 2 DESCRIPTION The disc is accelerated by applying a positive voltage to the spindle motor. No decisions are involved and the PLL is reset. No disc speed information is available for the microcontroller. The disc is accelerated as in start mode 1, however the PLL will monitor the disc speed. When the disc reaches 75% of its nominal speed, the controller will switch to jump mode. The motor status signals selectable via register 2 are valid. Motor servo enabled but FIFO kept reset at 50%, integrator is held. The audio is muted but it is possible to read the subcode. It should be noted that in the CD-ROM modes the data, on EBU and the I2S-bus is not muted. Similar to jump mode but motor integrator is kept at zero. Used for long jumps where there is a large change in disc speed. FIFO released after resetting to 50%. Audio mute released. Disc is braked by applying a negative voltage to the motor. No decisions are involved. The disc is braked as in stop mode 1 but the PLL will monitor the disc speed. As soon as the disc reaches 12% (or 6%, depending on the programmed brake percentage, via register E) of its nominal speed, the MOTSTOP status signal will go HIGH and switch the motor servo to Off mode. Motor not steered.
Jump mode
Jump mode 1 Play mode Stop mode 1 Stop mode 2
Off mode
MGA362 - 2
G
f4
f3
BW
f
Fig.19 Motor servo mode diagram.
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Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.14 7.14.1 Servo part DIODE SIGNAL PROCESSING
SAA7325
The photo detector in conventional two-stage three-beam Compact Disc systems normally contains six discrete diodes. Four of these diodes (three for single foucault systems) carry the Central Aperture signal (CA) while the other two diodes (satellite diodes) carry the radial tracking information. The CA signal is processed into an HF signal (for the decoder function) and LF signal (information for the focus servo loop) before it is supplied to the SAA7325. The analog signals from the central and satellite diodes are converted into a digital representation using Analog-to-Digital Converters (ADCs).
The ADCs are designed to convert unipolar currents into a digital code. The dynamic range of the input currents is adjustable within a given range, which is dependent on the value of the external reference current (Iref) resistor and the values programmed in shadow registers A and C. The magnitude of the signal currents for the central aperture diodes D1 to D4 and the radial diodes R1 and R2 are programmed separately to sixteen separate current ranges. The maximum input currents with an external 30 k reference current resistor are given in Table 10.
Table 12 Shadow register settings to control diode input current ranges SHADEN BIT 1 SHADOW REGISTER A signal magnitude control for diodes D1 to D4 ADDRESS 1010 DATA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 FUNCTION (0.042).Iref = 1.006 A (nom) (0.083).Iref = 2.013 A (nom) (0.125).Iref = 3.019 A (nom) (0.167).Iref = 4.025 A (nom) (0.208).Iref = 5.031 A (nom) (0.25).Iref = 6.034 A (nom) (0.292).Iref = 7.044 A (nom) (0.333).Iref = 8.05 A (nom) (0.375).Iref = 9.056 A (nom) (0.417).Iref = 10.063 A (nom) (0.458).Iref = 11.069 A (nom) (0.5).Iref = 12.075 A (nom) (0.542).Iref = 13.081 A (nom) (0.583).Iref = 14.088 A (nom) (0.625).Iref = 15.094 A (nom) (0.667).Iref = 16.1 A (nom) INITIAL - - - - - - - - - - - - - - - reset
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Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SHADEN BIT 1 SHADOW REGISTER C signal magnitude control for diodes R1 and R2 ADDRESS 1100 DATA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7.14.2 SIGNAL CONDITIONING FUNCTION (0.042).Iref = 1.006 A (nom) (0.083).Iref = 2.013 A (nom) (0.125).Iref = 3.019 A (nom) (0.167).Iref = 4.025 A (nom) (0.208).Iref = 5.031 A (nom) (0.25).Iref = 6.034 A (nom) (0.292).Iref = 7.044 A (nom) (0.333).Iref = 8.05 A (nom) (0.375).Iref = 9.056 A (nom)
SAA7325
INITIAL - - - - - - - - - - - - - - - reset
(0.417).Iref = 10.063 A (nom) (0.458).Iref = 11.069 A (nom) (0.5).Iref = 12.075 A (nom) (0.542).Iref = 13.081 A (nom) (0.583).Iref = 14.088 A (nom) (0.625).Iref = 15.094 A (nom) (0.667).Iref = 16.1 A (nom)
The digital codes retrieved from the ADCs are applied to logic circuitry to obtain the various control signals. The signals from the central aperture diodes are processed to obtain a normalised focus error signal. D1 - D2 D3 - D4 FE n = -------------------- - -------------------D1 + D2 D3 + D4 where the detector set-up is assumed to be as shown in Fig.20. In the event of single Foucault focusing method, the signal conditioning can be switched under software control such that the signal processing is as follows: D1 - D2 FE n = 2 x -------------------D1 + D2 The error signal, FEn, is further processed by a proportional integral and differential (PID) filter section. A Focus OK (FOK) flag is generated by means of the central aperture signal and an adjustable reference level. This signal is used to provide extra protection for the Track-Loss (TL) generation, the focus start-up procedure and the dropout detection.
The radial or tracking error signal is generated by the satellite detector signals R1 and R2. The radial error signal can be formulated as follows: RE s = ( R1 - R2 ) x re_gain + ( R1 + R2 ) x re_offset where the index `s' indicates the automatic scaling operation which is performed on the radial error signal. This scaling is necessary to avoid non-optimum dynamic range usage in the digital representation and reduces the radial bandwidth spread. Furthermore, the radial error signal will be made free from offset during start-up of the disc. The four signals from the central aperture detectors, together with the satellite detector signals generate a track position signal (TPI) which can be formulated as follows: TPI = sign[(D1 + D2 + D3 + D4) - (R1 + R2) x sum_gain] where the weighting factor sum_gain is generated internally by the SAA7325 during initialization.
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
handbook, full pagewidth
SATELLITE DIODE R1
SATELLITE DIODE R1
SATELLITE DIODE R1
D1 D3 D2
D2 D4
D1 D3
D1 D2 D3 D4
SATELLITE DIODE R2
SATELLITE DIODE R2
SATELLITE DIODE R2
single Foucault
astigmatic focus
double Foucault
MBG422
Fig.20 Detector arrangement.
7.14.3
FOCUS SERVO SYSTEM
7.14.3.2
Focus position control loop
7.14.3.1
Focus start-up
Five initially loaded coefficients influence the start-up behaviour of the focus controller. The automatically generated triangle voltage can be influenced by 3 parameters; for height (ramp_height) and DC offset (ramp_offset) of the triangle and its steepness (ramp_incr). For protection against false focus point detections two parameters are available which are an absolute level on the CA-signal (CA_start) and a level on the FEn signal (FE_start). When this CA level is reached the FOK signal becomes true. If the FOK signal is true and the level on the FEn signal is reached, the focus PID is enabled to switch on when the next zero crossing is detected in the FEn signal.
The focus control loop contains a digital PID controller which has 5 parameters which are available to the user. These coefficients influence the integrating (foc_int), proportional (foc_lead_length, part of foc_parm3) and differentiating (foc_pole_lead, part of foc_parm1) action of the PID and a digital low-pass filter (foc_pole_noise, part of foc_parm2) following the PID. The fifth coefficient foc_gain influences the loop gain.
7.14.3.3
Dropout detection
This detector can be influenced by one parameter (CA_drop). The FOK signal will become false and the integrator of the PID will hold if the CA signal drops below this programmable absolute CA level. When the FOK signal becomes false it is assumed, initially, to be caused by a black dot.
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.14.3.4 Focus loss detection and fast restart 7.14.4.3 Tracking control
SAA7325
Whenever FOK is false for longer than approximately 3 ms, it is assumed that the focus point is lost. A fast restart procedure is initiated which is capable of restarting the focus loop within 200 to 300 ms depending on the programmed coefficients of the microcontroller.
The actuator is controlled using a PID loop filter with user defined coefficients and gain. For stable operation between the tracks, the S-curve is extended over 0.75 of the track. On request from the microcontroller, S-curve extension over 2.25 tracks is used, automatically changing to access control when exceeding those 2.25 tracks. Both modes of S-curve extension make use of a track-count mechanism. In this mode, track counting results in an `automatic return-to-zero track', to avoid major music rhythm disturbances in the audio output for improved shock resistance. The sledge is continuously controlled, or provided with step pulses to reduce power consumption using the filtered value of the radial PID output. Alternatively, the microcontroller can read the average voltage on the radial actuator and provide the sledge with step pulses to reduce power consumption. Filter coefficients of the continuous sledge control can be preset by the user.
7.14.3.5
Focus loop gain switching
The gain of the focus control loop (foc_gain) can be multiplied by a factor of 2 or divided by a factor of 2 during normal operation. The integrator value of the PID is corrected accordingly. The differentiating (foc_pole_lead) action of the PID can be switched at the same time as the gain switching is performed.
7.14.3.6
Focus automatic gain control loop
The loop gain of the focus control loop can be corrected automatically to eliminate tolerances in the focus loop. This gain control injects a signal into the loop which is used to correct the loop gain. Since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). 7.14.4 RADIAL SERVO SYSTEM
7.14.4.4
Access
The access procedure is divided into two different modes (see Table 13), depending on the requested jump size. Table 13 Access modes ACCESS TYPE Actuator jump Sledge jump JUMP SIZE(1) 1 - brake_distance brake_distance - 32768 ACCESS SPEED decreasing velocity maximum power to sledge(1)
7.14.4.1
Level initialization
During start-up an automatic adjustment procedure is activated to set the values of the radial error gain (re_gain), offset (re_offset) and satellite sum gain (sum_gain) for TPI level generation. The initialization procedure runs in a radial open loop situation and is 300 ms. This start-up time period may coincide with the last part of the motor start-up time period: * Automatic gain adjustment: as a result of this initialization the amplitude of the RE signal is adjusted to within 10% around the nominal RE amplitude * Offset adjustment: the additional offset in RE due to the limited accuracy of the start-up procedure is less than 50 nm * TPI level generation: the accuracy of the initialization procedure is such that the duty factor range of TPI becomes 0.4 < duty factor < 0.6 (default duty factor = TPI HIGH/TPI period).
Note 1. Microcontroller presettable. The access procedure makes use of a track counting mechanism, a velocity signal based on a fixed number of tracks passed within a fixed time interval, a velocity set point calculated from the number of tracks to go and a user programmable parameter indicating the maximum sledge performance. If the number of tracks remaining is greater than the brake_distance then the sledge jump mode should be activated or, the actuator jump should be performed. The requested jump size together with the required sledge breaking distance at maximum access speed defines the brake_distance value.
7.14.4.2
Sledge control
The microcontroller can move the sledge in both directions via the steer sledge command.
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Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
During the actuator jump mode, velocity control with a PI controller is used for the actuator. The sledge is then continuously controlled using the filtered value of the radial PID output. All filter parameters (for actuator and sledge) are user programmable. In the sledge jump mode maximum power (user programmable) is applied to the sledge in the correct direction while the actuator becomes idle (the contents of the actuator integrator leaks to zero just after the sledge jump mode is initiated). The actuator can be electronically damped during sledge jump. The gain of the damping loop is controlled via the hold_mult parameter. Fast track jumping circuitry can be enabled/disabled via the xtra_preset parameter.
SAA7325
These signals are, however, afflicted with some uncertainties caused by: * Disc defects such as scratches and fingerprints * The HF information on the disc, which is considered as noise by the detector signals. In order to determine the spot position with sufficient accuracy, extra conditions are necessary to generate a Track Loss signal (TL) and an off-track counter value. These extra conditions influence the maximum speed and this implies that, internally, one of the following three counting states is selected: 1. Protected state: used in normal play situations. A good protection against false detection caused by disc defects is important in this state. 2. Slow counting state: used in low velocity track jump situations. In this state a fast response is important rather than the protection against disc defects (if the phase relationship between TL and RP of 12 radians is affected too much, the direction cannot then be determined accurately). 3. Fast counting state: used in high velocity track jump situations. Highest obtainable velocity is the most important feature in this state. 7.14.6 DEFECT DETECTION
7.14.4.5
Radial automatic gain control loop
The loop gain of the radial control loop can be corrected automatically to eliminate tolerances in the radial loop. This gain control injects a signal into the loop which is used to correct the loop gain. Since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). This gain control differs from the level initialization. The level initialization should be performed first. The disadvantage of using the level initialization without the gain control is that only tolerances from the front-end are reduced. 7.14.5 OFF-TRACK COUNTING
The track position signal (TPI) is a flag which is used to indicate whether the radial spot is positioned on the track, with a margin of 14 of the track-pitch. In combination with the radial polarity flag (RP) the relative spot position over the tracks can be determined.
A defect detection circuit is incorporated into the SAA7325. If a defect is detected, the radial and focus error signals may be zeroed, resulting in better playability. The defect detector can be switched off, applied only to focus control or applied to both focus and radial controls under software control (part of foc_parm1). The defect detector (see Fig.21) has programmable set points selectable by the parameter defect_parm.
handbook, full pagewidth
sat1
+ -
DECIMATION FILTER
FAST FILTER
SLOW FILTER
DEFECT GENERATION
PROGRAMMABLE HOLD-OFF
defect output
sat2
MBG421
Fig.21 Block diagram of defect detector.
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Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.14.7 OFF-TRACK DETECTION
SAA7325
Automatic error handling
7.14.8.3
During active radial tracking, off-track detection has been realised by continuously monitoring the off-track counter value. The off-track flag becomes valid whenever the off-track counter value is not equal to zero. Depending on the type of extended S-curve, the off-track counter is reset after 0.75 extend or at the original track in the 2.25 track extend mode. 7.14.8 HIGH-LEVEL FEATURES
Three Watchdogs are present: * Focus: detects focus drop out of longer than 3 ms, sets focus lost interrupt, switches off radial and sledge servos, disables drive to disc motor * Radial play: started when radial servo is in on-track mode and a first subcode frame is found; detects when maximum time between two subcode frames exceeds time set by playwatchtime parameter; then sets radial error interrupt, switches radial and sledge servos off, puts disc motor in jump mode * Radial jump: active when radial servo is in long jump or short jump modes. Detects when the off-track counter value decreases by less than 4 tracks between two readings (time interval set by jumpwatchtime parameter); then sets radial jump error, switches radial and sledge servos off to cancel jump The focus Watchdog is always active, the radial Watchdogs are selectable via the radcontrol parameter.
7.14.8.1
Interrupt mechanism and STATUS pin
The STATUS pin is an output which is active LOW, its output is selected by decoder register 7 to be either the decoder status bit (active LOW) selected by decoder register 2 (only available in 4-wire bus mode) or the interrupt signal generated by the servo part. 8 signals from the interrupt status register are selectable from the servo part via the interrupt_mask parameter. The interrupt is reset by sending the read high-level status command. The 8 signals are as follows: * Focus lost: dropout of longer than 3 ms * Subcode ready * Subcode absolute seconds changed * Subcode discontinuity detected: new subcode time before previous subcode time, or more than 10 frames later than previous subcode time * Radial error: during radial on-track, no new subcode frame occurs within time defined by the playwatchtime parameter; during radial jump, less than 4 tracks have been crossed during time defined by the jumpwatchtime parameter * Autosequencer state change * Autosequencer error * Subcode interface blocked: the internal decoder interface is being used. It should be noted that if the STATUS pin output is selected via decoder register 2 and either the microcontroller writes a different value to decoder register 2 or the decoder interface is enabled then the STATUS output will change.
7.14.8.4
Automatic sequencers and timer interrupts
Two automatic sequencers are implemented (and must be initialized after power-on): * Autostart sequencer: controls the start-up of focus, radial and motor * Autostop sequencer: brakes the disc and shuts down servos. When the automatic sequencers are not used it is possible to generate timer interrupts, defined by the time_parameter coefficient.
7.14.8.5
High-level status
The read high-level status command can be used to obtain the interrupt, decoder, autosequencer status registers and the motor start time. Use of the read high-level status command clears the interrupt status register, and re-enables the subcode read via a servo command. 7.14.9 DRIVER INTERFACE
7.14.8.2
Decoder interface
The decoder interface allows decoder registers 0 to F to be programmed and subcode Q-channel data to be read via servo commands. The interface is enabled/disabled by the preset latch command (and the xtra_preset parameter).
The control signals (pins RA, FO and SL) for the mechanism actuators are pulse density modulated. The modulating frequency can be set to either 1.0584 (DSD mode) or 2.1168 MHz; controlled via the xtra_preset parameter. An analog representation of the output signals can be achieved by connecting a 1st-order low-pass filter to the outputs.
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
During reset (i.e. RESET pin is held LOW) the RA, FO and SL pins are high-impedance. 7.14.10 LASER INTERFACE The LDON pin (open-drain output) is used to switch the laser off and on. When the laser is on, the output is high-impedance. The action of the LDON pin is controlled by the xtra_preset parameter; the pin is automatically driven if the focus control loop is active. 7.14.11 RADIAL SHOCK DETECTOR The shock detector (see Fig.22) can be switched on during normal track following, and detects within an adjustable frequency whether disturbances in the radial spot position relative to the track exceed an adjustable level (controlled by shock_level).
SAA7325
Every time the radial tracking error (RE) exceeds this level the radial control bandwidth is switched to twice its original bandwidth and the loop gain is increased by a factor of 4. The shock detection level is adjustable in 16 steps from 0% to 100% of the traverse radial amplitude which is sent to an amplitude detection unit via an adjustable band-pass filter (controlled by sledge_parm1); lower corner frequency can be set at either 0 or 20 Hz, and upper corner frequency at 750 or 1850 Hz. The shock detector is switched off automatically during jump mode.
handbook, full pagewidth
RE
HIGH-PASS FILTER (0 or 20 Hz)
LOW-PASS FILTER (750 or 1850 Hz)
AMPLITUDE DETECTION
SHOCK OUTPUT
MGC914
Fig.22 Block diagram of radial shock detector.
7.15
Microcontroller interface
Communication on the microcontroller interface can be set-up in two different modes: * 4-wire bus mode: protocol compatible with SAA7345 (CD6) and TDA1301 (DSIC2) where: - SCL = serial clock - SDA = serial data - RAB = R/W control and data strobe (active HIGH) for writing to decoder registers 0 to F, reading status bit selected via decoder register 2 and reading Q-channel subcode - SILD = R/W control and data strobe (active LOW) for servo commands.
* I2C-bus mode: I2C-bus protocol where SAA7325 behaves as slave device, activated by setting RAB = HIGH and SILD = LOW where: - I2C-bus slave address (write mode) = 30H - I2C-bus slave address (read mode) = 31H - Maximum data transfer rate = 400 kbits/s. It should be noted that only servo commands can be used therefore, writing to decoder registers 0 to F, reading decoder status and reading Q-channel subcode data must be performed by servo commands.
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.15.1 MICROCONTROLLER INTERFACE (4-WIRE BUS MODE)
SAA7325
Reading Q-channel subcode
7.15.1.4
7.15.1.1
Writing data to registers 0 to F
The sixteen 4-bit programmable configuration registers, 0 to F (see Table 14), can be written to via the microcontroller interface using the protocol shown in Fig.23. It should be noted that SILD must be held HIGH; A3 to A0 identifies the register number and D3 to D0 is the data; the data is latched into the register on the LOW-to-HIGH transition of RAB.
To read the Q-channel subcode direct in the 4-wire bus mode, the SUBQREADY-I signal should be selected as the status signal. The subcode read protocol is illustrated in Fig.26. It should be noted that SILD must be held HIGH; after subcode read starts, the microcontroller may take as long as it wants to terminate the read operation. When enough subcode has been read (1 to 96 bits), terminate reading by pulling RAB LOW. Alternatively, the Q-channel subcode can be read using a servo command as follows: * Use the read high-level status command to monitor the subcode ready signal * Send the read subcode command, and read the required number of bytes (up to 12) * Send the read high-level status command; to re-enable the decoder interface.
7.15.1.2
Writing repeated data to registers 0 to F
The same data can be repeated several times (e.g. for a fade function) by applying extra RAB pulses as shown in Fig.24. It should be noted that SCL must stay HIGH between RAB pulses.
7.15.1.3
Reading decoder status information on SDA
There are several internal status signals, selected via register 2, which can be made available on the SDA line: SUBQREADY-I: LOW if new subcode word is ready in Q-channel register MOTSTART1: HIGH if motor is turning at 75% or more of nominal speed MOTSTART2: HIGH if motor is turning at 50% or more of nominal speed MOTSTOP: HIGH if motor is turning at 12% or less of nominal speed; can be set to indicate 6% or less (instead of 12% or less) via register E PLL lock: HIGH if sync coincidence signals are found V1: follows input on pin V1 V2: follows input on pin V2 MOTOR-OV: HIGH if the motor servo output stage saturates FIFO-OV: HIGH if FIFO overflows SHOCK: MOTSTART2 + PLL Lock + MOTOR-OV + FIFO-OV + servo interrupt signal + OTD (HIGH if shock detected) LA-SHOCK: latched SHOCK signal. The status read protocol is shown in Fig.25. It should be noted that SILD must be held HIGH.
7.15.1.5
Behaviour of the SUBQREADY-I signal
When the CRC of the Q-channel word is good, and no subcode is being read, the SUBQREADY-I status signal will react as shown in Fig.27. When the CRC is good and the subcode is being read, the timing in Fig.28 applies. If t1 (SUBQREADY-I status LOW to end of subcode read) is below 2.6/n ms, then t2 = 13.1/n ms (i.e. the microcontroller can read all subcode frames if it completes the read operation within 2.6/n ms after the subcode is ready). If these criteria are not met, it is only possible to guarantee that t3 will be below 26.2/n ms (approximately). If subcode frames with failed CRCs are present, the t2 and t3 times will be increased by 13.1/n ms for each defective subcode frame. It should be noted that in the lock-to-disc mode `n' is replaced by `d', which is the disc speed factor.
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.15.1.6 Write servo commands
SAA7325
A write data command is used to transfer data (a number of bytes) from the microcontroller, using the protocol shown in Fig.29. The first of these bytes is the command byte and the following are data bytes; the number (between 1 and 7) depends on the command byte. It should be noted that RAB must be held LOW; the command or data is interpreted by the SAA7325 after the HIGH-to-LOW transition of SILD; there must be a minimum time of 70 s between SILD pulses.
The sequence for a write data command (that requires 3 data bytes) is as follows: 1. Send START condition 2. Send address 30H (write) 3. Write command byte 4. Write data byte 1 5. Write data byte 2 6. Write data byte 3 7. Send STOP condition. It should be noted that more than one command can be sent in one write sequence. The sequence for a read data command (that reads 2 data bytes) is as follows: 1. Send START condition 2. Send address 30H (write) 3. Write command byte 4. Send STOP condition 5. Send START condition 6. Send address 31H (read) 7. Read data byte 1 8. Read data byte 2 9. Send STOP condition. It should be noted that the timing constraints specified for the read and write servo commands must still be adhered to.
7.15.1.7
Writing repeated data in servo commands
The same data byte can be repeated by applying extra SILD pulses as illustrated in Fig.30. SCL must be HIGH between the SILD pulses.
7.15.1.8
Read servo commands
A read data command is used to transfer data (status information) to the microcontroller, using the protocol shown in Fig.31. The first byte written determines the type of command. After this byte a variable number of bytes can be read. It should be noted that RAB must be held LOW; after the end of the command byte (LOW-to-HIGH transition on SILD) there must be a delay of 70 s before reading data is started (i.e. the next HIGH-to-LOW transition on SILD); there must be a minimum time of 70 s between SILD pulses. 7.15.2 MICROCONTROLLER INTERFACE (I2C-BUS MODE)
Bytes are transferred over the interface in groups (i.e. servo commands) of which there are two types: write data commands and read data commands.
RAB (microcontroller) SCL (microcontroller) SDA (microcontroller) SDA (SAA7325) A3 A2 A1 A0 D3 D2 D1 D0
high-impedance
MGL683
Fig.23 Microcontroller write protocol for registers 0 to F.
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
RAB (microcontroller) SCL (microcontroller) SDA (microcontroller) SDA (SAA7325) A3 A2 A1 A0 D3 D2 D1 D0
high-impedance
MGL684
Fig.24 Microcontroller write protocol for registers 0 to F (repeat mode).
RAB (microcontroller) SCL (microcontroller) SDA (microcontroller) SDA (SAA7325)
high-impedance STATUS
MGL685
Fig.25 Microcontroller read protocol for decoder status on SDA.
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
RAB (microcontroller) SCL (microcontroller) SDA (SAA7325) STATUS CRC OK Q1 Q2 Q3 Qn - 2 Qn - 1 Qn
MGL686
Fig.26 Microcontroller protocol for reading Q-channel subcode.
RAB (microcontroller) SCL (microcontroller) high-impedance
SDA (SAA7325)
CRC OK
CRC OK
10.8/n ms
15.4/n ms 2.3/n ms
MGL687
READ start allowed
Fig.27 SUBQREADY-I status timing when no subcode is read.
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
t2 t1 RAB (microcontroller) SCL (microcontroller) SDA (SAA7325) Q1 Q2 Q3 Qn
MGL688
t3
Fig.28 SUBQREADY-I status timing when subcode is read.
SILD handbook, full pagewidth (microcontroller) SCL (microcontroller) SDA (microcontroller) SDA (SAA7325) high-impedance microcontroller write (one byte: command or data) SILD (microcontroller) SDA (microcontroller) COMMAND DATA1 DATA2 DATA3
MGL689
D7
D6
D5
D4
D3
D2
D1
D0
command or data byte
microcontroller write (full command)
Fig.29 Microcontroller protocol for write servo commands.
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
handbook, full pagewidth
SILD (microcontroller) SDA (microcontroller) COMMAND DATA1
MBG413
microcontroller write (full command)
Fig.30 Microcontroller protocol for repeated data in write servo commands.
handbook, full pagewidth
SILD (microcontroller) SCL (microcontroller)
SDA (SAA7325)
D7
D6
D5
D4
D3 data byte
D2
D1
D0
microcontroller read (one data byte) SILD (microcontroller) SDA (SAA7325) SDA (microcontroller) COMMAND
MGL690
DATA1
DATA2
DATA3
microcontroller read (full command)
Fig.31 Microcontroller protocol for read servo commands.
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Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.15.3 DECODER REGISTERS AND SHADOW REGISTERS
SAA7325
To maintain compatibility with the SAA737x series, decoder registers 0 to F are identical to SAA7370. However, to control the extra functionality of SAA7325, a new set of registers called shadow registers have been implemented. These are accessed by using the LSB of decoder register F. This bit is called SHADEN (shadow registers enable) on SAA7325. When this bit is set to logic 1 (i.e. decoder register F set to XXX1), any subsequent addresses will be decoded by the shadow registers. In fact, only four addresses are implemented as shadow registers; 3, 7, A and C. Any other addresses sent while SHADEN = 1 are invalid and have no effect. 7.15.4
When SHADEN is set to logic 0 (decoder register F set to XXX0) all subsequent addresses are decoded by the main decoder registers again. Access to decoder register F is always enabled so that SHADEN can be set or reset as required. The SHADEN bit and subsequent shadow registers are programmed identically to the main decoder registers, i.e. they can be directly programmed when using SAA7325 in 4-wire mode or programmed via the servo interface when using 3-wire or I2C-bus modes. The main decoder registers are shown in Table 14. The functions implemented using shadow registers are shown in Table 16.
SUMMARY OF FUNCTIONS CONTROLLED BY DECODER REGISTERS 0 TO F
Table 14 Registers 0 to F REGISTER 0 (fade and attenuation) ADDRESS 0000 DATA 0000 0010 0001 0100 0101 1 (motor mode) 0001 X000 X001 X010 X011 X100 X101 X111 X110 1XXX 0XXX mute attenuate full-scale step down step up motor off mode motor stop mode 1 motor stop mode 2 motor start mode 1 motor start mode 2 motor jump mode motor play mode motor jump mode 1 anti-windup active anti-windup off FUNCTION INITIAL(1) reset - - - - reset - - - - - - - - reset
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Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
REGISTER 2 (status control to servo part not the STATUS pin) ADDRESS 0010 DATA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 3 (DAC output) 0011 1010 1011 1100 1111 1110 0000 0011 0010 0100 0111 0110 4 (motor gain) 0100 X000 X001 X010 X011 X100 X101 X110 X111 0XXX 1XXX 5 (motor bandwidth) 0101 XX00 XX01 XX10 XX11 00XX 01XX 10XX 1999 Jun 17 FUNCTION status = SUBQREADY-I status = MOTSTART1 status = MOTSTART2 status = MOTSTOP status = PLL lock status = V1 status = V2 status = MOTOR-OV status = FIFO overflow status = shock detect status = latched shock detect status = latched shock detect reset I2S-bus; CD-ROM mode EIAJ; CD-ROM mode I2S-bus; I2S-bus; 18-bit; 4fs mode 16-bit; fs mode I2S-bus; 18-bit; 2fs mode EIAJ; 16-bit; 4fs EIAJ; 16-bit; 2fs EIAJ; 16-bit; fs EIAJ; 18-bit; 4fs EIAJ; 18-bit; 2fs EIAJ; 18-bit; fs motor gain G = 3.2 motor gain G = 4.0 motor gain G = 6.4 motor gain G = 8.0 motor gain G = 12.8 motor gain G = 16.0 motor gain G = 25.6 motor gain G = 32.0 disable comparator clock divider enable comparator clock divider; only if SELLPLL set HIGH motor f4 = 0.5 Hz motor f4 = 0.7 Hz motor f4 = 1.4 Hz motor f4 = 2.8 Hz motor f3 = 0.85 Hz motor f3 = 1.71 Hz motor f3 = 3.42 Hz 40
SAA7325
INITIAL(1) reset - - - - - - - - - - - - - reset - - - - - - - - reset - - - - - - - reset - reset - - - reset - -
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
REGISTER 6 (motor output configuration) ADDRESS 0110 DATA XX00 XX01 XX10 XX11 00XX 01XX 10XX 11XX 7 (DAC output and status control) 0111 XX00 XX10 X0XX X1XX 0XXX 1XXX 8 (PLL loop filter bandwidth) 9 (PLL equalization) 1001 0011 0001 0010 0100 0101 A (EBU output) 1010 XX0X XX1X X0X0 X0X1 X1X0 X1X1 0XXX 1XXX B (operating frequency) 1011 00XX 01XX 0X00 0X10 0X11 FUNCTION motor power maximum 37% motor power maximum 50% motor power maximum 75% motor power maximum 100% MOTO1, MOTO2 pins 3-state motor PWM mode motor PDM mode motor CDV mode interrupt signal from servo at STATUS pin status bit from decoder status register at STATUS pin DAC data normal value DAC data inverted value left channel first at DAC (WCLK normal) right channel first at DAC (WCLK inverted) see Table 15
SAA7325
INITIAL(1) reset - - - reset - - - reset - reset - reset - -
PLL loop filter equalization PLL 30 ns over-equalization PLL 15 ns over-equalization PLL 15 ns under-equalization PLL 30 ns under-equalization EBU data before concealment EBU data after concealment and fade level II clock accuracy (<1000 ppm) level I clock accuracy (<50 ppm) level III clock accuracy (>1000 ppm) EBU off - output low flags in EBU off flags in EBU on 33.8688 MHz crystal present, or 8.4672 MHz (or 16.9344 MHz) crystal with SELPLL set HIGH 16.9344 MHz crystal present standby 1: `CD-STOP' mode standby 2: `CD-PAUSE' mode operating mode
reset - - - - - reset reset - - - reset - reset - reset - -
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
REGISTER C (versatile pins interface) ADDRESS 1100 DATA XXX1 XXX0 XX0X 001X 011X D (versatile pins interface) 1101 0000 XX01 XX10 XX11 01XX 10XX 11XX E 1110 00XX 01XX XX0X XX1X XXX0 XXX1 F (subcode interface and shadow register enable) 1111 X0XX X1XX 0XXX 1XXX XXX0 FUNCTION external off-track signal input at V1 internal off-track signal used (V1 may be read via status) kill-L at KILL output, kill-R at V3 output V3 = 0; single KILL output V3 = 1; single KILL output 4-line motor (using V4 and V5) Q-to-W subcode at V4 V4 = 0 V4 = 1 de-emphasis signal at V5, no internal de-emphasis filter V5 = 0 V5 = 1 audio features disabled audio features enabled lock-to-disc mode disabled lock-to-disc mode enabled motor brakes to 12% motor brakes to 6% subcode interface off subcode interface on 4-wire subcode 3-wire subcode SHADEN = 0; shadow registers not enabled; addresses will be decoded by main decoder registers SHADEN = 1; shadow registers enabled; all subsequent addresses will be decoded by shadow registers, not decoder registers
SAA7325
INITIAL(1) - reset - reset - - - - reset - - reset - reset reset - reset - reset - reset - reset
XXX1
-
Note 1. The initial column shows the Power-on reset state.
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
Table 15 Loop filter bandwidth FUNCTION REGISTER ADDRESS DATA LOOP BANDWIDTH (Hz) 1640 3279 6560 1640 3279 6560 1640 3279 6560 1640 3279 6560 INTERNAL BANDWIDTH (Hz) 525 263 131 1050 525 263 2101 1050 525 4200 2101 1050 LOW-PASS BANDWIDTH (Hz) 8400 16800 33600 8400 16800 33600 8400 16800 33600 8400 16800 33600
SAA7325
INITIAL(1)
8 (PLL loop filter bandwidth)
1000
0000 0001 0010 0100 0101 0110 1000 1001 1010 1100 1101 1110
- - - - - - - reset - - - -
Note 1. The initial column shows the Power-on reset state. 7.15.5 SUMMARY OF FUNCTIONS CONTROLLED BY SHADOW REGISTERS
Table 16 Shadow register settings SHADEN BIT 1 SHADOW REGISTER 3 control of versatile and clock pins ADDRESS 0011 DATA XXX0 XXX1 XX0X XX1X X0XX X1XX 0XXX 1XXX 7 control of onboard DAC 0111 XXX0 XXX1 XX0X XX1X 7 servo reference pin 7, VRIN X1XX X0XX FUNCTION select CL4 on CL11/4 output select CL11 on CL11/4 output enable CL11/4 output pin set CL11/4 output pin to high-impedance enable CL16 output pin set CL16 output pin to high-impedance V2/V3 pin configured as V2 input V2/V3 pin configured as V3 output (open-drain) hold onboard DAC outputs at zero enable onboard DAC outputs use external DAC or route audio data into onboard DAC (loopback mode) route audio data into onboard DAC (non-loopback mode) use internal reference for servo reference voltage use external reference for servo reference voltage INITIAL reset - reset - reset - reset - reset - reset - reset -
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Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SHADEN BIT 1 SHADOW REGISTER A signal magnitude control for diodes D1 to D4 ADDRESS 1010 DATA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1 C Signal magnitude control for diodes R1 and R2 1100 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 FUNCTION (0.042).Iref = 1.006 A (nom) (0.083).Iref = 2.013 A (nom) (0.125).Iref = 3.019 A (nom) (0.167).Iref = 4.025 A (nom) (0.208).Iref = 5.031 A (nom) (0.25).Iref = 6.034 A (nom) (0.292).Iref = 7.044 A (nom) (0.333).Iref = 8.05 A (nom) (0.375).Iref = 9.056 A (nom) (0.417).Iref = 10.063 A (nom) (0.458).Iref = 11.069 A (nom) (0.5).Iref = 12.075 A (nom) (0.542).Iref = 13.081 A (nom) (0.583).Iref = 14.088 A (nom) (0.625).Iref = 15.094 A (nom) (0.667).Iref = 16.1 A (nom) (0.042).Iref = 1.006 A (nom) (0.083).Iref = 2.013 A (nom) (0.125).Iref = 3.019 A (nom) (0.167).Iref = 4.025 A (nom) (0.208).Iref = 5.031 A (nom) (0.25).Iref = 6.034 A (nom) (0.292).Iref = 7.044 A (nom) (0.333).Iref = 8.05 A (nom) (0.375).Iref = 9.056 A (nom) (0.417).Iref = 10.063 A (nom) (0.458).Iref = 11.069 A (nom) (0.5).Iref = 12.075 A (nom) (0.542).Iref = 13.081 A (nom) (0.583).Iref = 14.088 A (nom) (0.625).Iref = 15.094 A (nom) (0.667).Iref = 16.1 A (nom)
SAA7325
INITIAL - - - - - - - - - - - - - - - reset - - - - - - - - - - - - - - - reset
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Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.15.6 SUMMARY OF SERVO COMMANDS
SAA7325
A list of the servo commands are given in Table 17. These are fully compatible with SAA7370. Table 17 SAA7325 servo commands COMMANDS Write commands Write_focus_coefs1 Write_focus_coefs2 Write_focus_command Focus_gain_up Focus_gain_down Write_radial coefs Preset_Latch Radial_off Radial_init Short_jump Long_jump Steer_sledge Preset_init Write_decoder_reg(1) Write_parameter Read commands Read_Q_subcode(1)(2) Read_status Read_hilevel_status(3) Read_aux_status Notes 1. These commands only available when internal decoder interface is enabled. 2. and bytes are clocked out LSB first. 3. Decoder status flag information in is only valid when the internal decoder interface is enabled. 0H 70H E0H F0H up to 12 up to 5 up to 4 up to 3 17H 27H 33H 42H 62H 57H 81H C1H C1H C3H C5H B1H 93H D1H A2H 7 7 3 2 2 7 1 1 1 3 5 1 3 1 2 `1CH' `3CH' CODE BYTES PARAMETERS
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Philips Semiconductors
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Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
7.15.7 SUMMARY OF SERVO COMMAND PARAMETERS
SAA7325
Table 18 Servo command parameters PARAMETER foc_parm_1 foc_parm_2 foc_parm_3 foc_int foc_gain CA_drop ramp_offset ramp_height ramp_incr FE_start rad_parm_play rad_pole_noise rad_length_lead rad_int rad_gain rad_parm_jump vel_parm1 vel_parm2 speed_threshold hold_mult brake_dist_max sledge_long_brake sledge_Umax sledge_level sledge_parm_1 sledge_parm_2 RAM ADDRESS - - - 14H 15H 12H 16H 18H - 19H 28H 29H 1CH 1EH 2AH 27H 1FH 32H 48H 49H 21H 58H - - 36H 17H AFFECTS focus PID focus PID focus PID focus PID focus PID focus PID focus ramp focus ramp focus ramp focus ramp radial PID radial PID radial PID radial PID radial PID radial jump radial jump radial jump radial jump radial jump radial jump radial jump sledge sledge sledge sledge POR VALUE - - - - 70H - - - - - - - - - 70H - - - - 00H - FFH - - - - DETERMINES end of focus lead defect detector enabling focus low-pass focus error normalising focus lead length minimum light level focus integrator crossover frequency focus PID loop gain sensitivity of drop-out detector asymmetry of focus ramp peak-to-peak value of ramp voltage slope of ramp voltage minimum value of focus error end of radial lead radial low-pass length of radial lead radial integrator crossover frequency radial loop gain filter during jump PI controller crossover frequencies jump pre-defined profile maximum speed in fastrad mode electronic damping sledge bandwidth during jump maximum sledge distance allowed in fast actuator steered mode brake distance of sledge voltage on sledge during long jump voltage on sledge when steered sledge integrator crossover frequency sledge low-pass frequencies sledge gain sledge operation mode sledge_pulse1 sledge_pulse2 defect_parm shock_level playwatchtime 1999 Jun 17 46H 64H - - 54H pulsed sledge pulsed sledge defect detector shock detector Watchdog 46 - - - - - pulse width pulse height defect detector setting shock detector operation radial on-track Watchdog time
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
PARAMETER jumpwatchtime radcontrol chip_init xtra_preset RAM ADDRESS 57H 59H - 4AH AFFECTS Watchdog Watchdog set-up set-up POR VALUE - - - 38H
SAA7325
DETERMINES radial jump Watchdog time-out enable/disable automatic radial off feature enable/disable decoder interface laser on/off RA, FO and SL PDM modulating frequency fast jumping circuit on/off
cd6cmd interrupt_mask seq_control focus_start_time motor_start_time1 motor_start_time2 radial_init_time brake_time RadCmdByte osc_inc phase_shift level1 level2 agc_gain
4DH 53H 42H 5EH 5FH 60H 61H 62H 63H 68H 67H 69H 6AH 6CH
decoder interface STATUS pin autosequencer autosequencer autosequencer autosequencer autosequencer autosequencer autosequencer focus/radial AGC focus/radial AGC focus/radial AGC focus/radial AGC focus/radial AGC
- - - - - - - - - - - - - -
decoder part commands enabled interrupts autosequencer control focus start time motor start 1 time motor start 2 time radial initialization time brake time radial command byte AGC control frequency of injected signal phase shift of injected signal amplitude of signal injected amplitude of signal injected focus/radial gain
1999 Jun 17
47
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI(max) PARAMETER supply voltage maximum input voltage any input pins SDA, SCL, RAB and SILD VO VDD(diff) IO II(d) Ves Tamb Tstg Notes output voltage (any output) difference between VDDA, VDDD and Vpos output current (continuous) DC input diode current (continuous) electrostatic handling ambient temperature storage temperature note 2 note 3 -0.5 -0.5 -0.5 - - - -2000 -200 -10 -55 CONDITIONS note 1 MIN. -0.5
SAA7325
MAX. +3.6 VDD + 0.5 +5.5 +3.6 0.25 20 20 +2000 +200 +70 +125
UNIT V V V V V mA mA V V C C
1. All VDD (and Vpos) connections and VSS (and Vneg) connections must be made externally to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor with a rise time of 15 ns. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor. 9 CHARACTERISTICS VDD = 3.0 to 3.6 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL Supply VDD IDD supply voltage supply current VDD = 3.3 V 3.0 - 3.3 20 3.6 - V mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Bitstream DAC output (VDDD = 3.3 V, Vpos = 3.3 V; VSS = 0 V, Vneg = 0 V; Tamb = 25 C) DIFFERENTIAL OUTPUTS: PINS LN, LP, RN AND RP S/N signal-to-noise ratio note 1 at 0 dB; note 1 -85 - -90 -83 - -80 dB dB (THD + N)/S total harmonic distortion plus noise-to-signal ratio
Servo and decoder analog functions (VDDA = 3.3 V; VSSA = 0 V; Tamb = 25 C) REFERENCE GENERATOR: PIN Iref VIref Iref RIref reference voltage level input reference current external resistor 0.6 - - 0.7245 24.15 30 0.8 - - V A k
1999 Jun 17
48
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA7325
MAX.
UNIT
Decoder analog front-end (VDDA = 3.3 V; VSSA = 0 V; Tamb = 25 C) COMPARATOR INPUTS: PINS HFIN AND HFREF fclk Vth(sw) VHFIN clock frequency switching voltage threshold input voltage level (HFIN) note 2 8 - - - 0.5VDD 1.0 70 - - MHz V V
Servo analog part (VDDA = 3.3 V; VSSA = 0 V; Tamb = 25 C; RIref = 30 k) PINS D1 TO D4; R1 AND R2 ID(max) IR(max) VRIN maximum input current for central diode input signal maximum input current for satellite diode input signal internally generated reference voltage externally generated reference voltage applied to VRIN (pin 7) (THD + N)/S total harmonic distortion plus noise-to-signal ratio S/N PSRR Gtol Gv cs Digital inputs
PINS
note 3 note 3 note 4 note 4
4.025 4.025 - 0.5
- - 0.75 -
16.1 16.1 -
A A V
0.5VDD + 0.1 V
at 0 dB; note 5
- -
-50 55 45 0 - 60
-45 - - +20 2 -
dB dB dB % % dB
signal-to-noise ratio power supply ripple rejection at VDDA2 gain tolerance variation of gain between channels channel separation note 6 note 7
- -20 - -
RESET AND V1 (CMOS INPUT WITH PULL-UP RESISTOR AND HYSTERESIS) switching voltage threshold rising switching voltage threshold falling hysteresis voltage input pull-up resistance input capacitance reset pulse width (active LOW) RESET only Vi = 0 V - 0.2VDDD 1.35 - - 1 - - 1.65 160 - - 0.8VDDD - - - 10 - V V V k pF s
Vthr(sw) Vthf(sw) Vhys Ri(pu) Ci tresL
PIN
SELPLL (CMOS INPUT WITH PULL-UP RESISTOR) LOW-level input voltage HIGH-level input voltage input pull-up resistance input capacitance 49 Vi = 0 V -0.3 0.7VDDD - - - - 160 - +0.3VDDD VDDD + 0.3 - 10 V V k pF
VIL VIH Ri(pu) Ci 1999 Jun 17
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SYMBOL
PINS
SAA7325
PARAMETER
CONDITIONS
MIN. -0.3 0.7VDDD - -
TYP.
MAX.
UNIT
TEST1, TEST2 AND TEST3 (CMOS INPUT WITH PULL-DOWN RESISTORS) LOW-level input voltage HIGH-level input voltage input pull-up resistance input capacitance RCK, WCLI, SDI AND SCLI (CMOS INPUTS) LOW-level input voltage HIGH-level input voltage input leakage current input capacitance SCL, SILD AND RAB (5 V TOLERANT CMOS INPUTS) LOW-level input voltage HIGH-level input voltage input leakage current input capacitance Vi = 0 - VDDD -0.3 0.8VDDD -10 - - - - - +0.2VDDD 5.5 +10 10 V V A pF Vi = 0 - VDDD -0.3 0.7VDDD -10 - - - - - +0.3VDDD VDDD + 0.3 +10 10 V V A pF Vi = VDDD +0.3VDDD VDDD + 0.3 - 10 V V k pF
VIL VIH Ri(pu) Ci
PINS
- -
160 -
VIL VIH ILI Ci
PINS
VIL VIH ILI Ci
Digital outputs
PINS
V4 AND V5 LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time CL = 20 pF; 0.4 V - (VDDD - 0.4) CL = 20 pF; (VDDD - 0.4) - 0.4 V IOL = 4 mA IOH = -4 mA 0 VDDD - 0.4 - - - - - - - - 0.4 VDDD 100 10 10 V V pF ns ns
VOL VOH CL to(r) to(f)
Open-drain outputs
PINS
CFLG, STATUS, KILL AND LDON (OPEN-DRAIN OUTPUT) LOW-level output voltage LOW-level output current load capacitance output fall time CL = 50 pF; (VDDD - 0.4) - 0.4 V IOL = 1 mA 0 - - - - - - - 0.4 2 50 30 V mA pF ns
VOL IOL CL to(f)
3-state outputs
PINS
EF, SCLK, WCLK, DATA, CL16, RA, FO, SL, SBSY, SFSY, SUB AND CL11/4 LOW-level output voltage HIGH-level output voltage load capacitance output rise time CL = 20 pF; 0.4 V to (VDDD - 0.4) IOL = 1 mA IOH = -1 mA 0 VDDD - 0.4 - - - - - - 0.4 VDDD 35 15 V V pF ns
VOL VOH CL to(r)
1999 Jun 17
50
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SYMBOL to(f) IZO PARAMETER output fall time output 3-state leakage current CONDITIONS CL = 20 pF; (VDDD - 0.4) to 0.4 V Vi = 0 - VDD - -10 MIN. - - TYP. 15 +10
SAA7325
MAX.
UNIT ns A
(WHEN CL11/4 IS CONFIGURED AS CL11 OUTPUT) tOH output HIGH time (relative to clock period) Vo = 1.5 V 45 50 55 %
MOTO1, MOTO2 AND DOBM VOL VOH CL to(r) to(f) IZO LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time output 3-state leakage current CL = 20 pF; 0.4 V - (VDDD - 0.4) CL = 20 pF; (VDDD - 0.4) - 0.4 V Vi = 0 - VDD IOL = 4 mA IOH = -4 mA 0 VDDD - 0.4 - - - -10 - - - - - - 0.4 VDD 100 10 10 +10 V V pF ns ns A
Digital input/output
PIN
SDA (5 V TOLERANT CMOS INPUT/OPEN-DRAIN I2C-BUS OUTPUT) LOW-level input voltage HIGH-level input voltage 3-state leakage current input capacitance LOW-level output voltage LOW-level output current load capacitance output fall time CL = 20 pF; 0.85VDDD - 0.4 IOL = 2 mA Vi = 0 - VDDD -0.3 0.8VDDD -10 - 0 - - - - - - - - - - - +0.2VDDD 5.5 +10 10 0.4 6 50 15 V V A pF V mA pF ns
VIL VIH IZO Ci VOL IOL CL to(f)
PIN
V2/V3 (CMOS INPUT WITH PULL-UP RESISTOR AND HYSTERESIS/OPEN-DRAIN OUTPUT) switching voltage threshold rising switching voltage threshold falling hysteresis voltage input pull-up resistance input capacitance LOW-level output voltage LOW-level output current load capacitance output fall time CL = 20 pF; (VDDD - 0.4) - 0.4 V IOL = 1 mA Vi = 0 V - 0.2VDDD 1.35 - - 0 - - - - - 1.65 120 - - - - - 0.8VDDD - - - 10 0.4 1 25 15 V V V k pF V mA pF ns
Vthr(sw) Vthf(sw) Vhys Ri(pu) Ci VOL IOL CL to(f)
1999 Jun 17
51
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SYMBOL Crystal oscillator INPUT: CRIN (EXTERNAL CLOCK) VIL VIH ILI Ci fxtal gm Cfb Co Notes 1. Assumes use of external components as shown in the application diagram (Figs 38 or 39). 2. Highest clock frequency at which data slicer produces 1010 output in analog self-test mode. LOW-level input voltage HIGH-level input voltage input leakage current input capacitance -0.3 0.8VDD -10 - 8 - - - - - - - 8.4672 30 - - PARAMETER CONDITIONS MIN. TYP.
SAA7325
MAX.
UNIT
+0.2VDD VDD + 0.3 +10 10
V V A pF
OUTPUT: CROUT; see Figs 3 and 4 crystal frequency mutual conductance at start-up feedback capacitance output capacitance 35 - 5 10 MHz mA/V pF pF
3. The maximum input current depends on the value of the external resistor connected to Iref and the settings of shadow registers A and C: a) With RIref = 30 k, minimum Imax = Iref/6 (24.15 A)/6 = 4.025 A. b) With RIref = 30 k, maximum Imax = 2 x Iref/3 2/3 x (24.15 A) = 16.1 A. 4. VRIN can be set to an internal source or an externally applied reference voltage using shadow register 7. 5. Measuring bandwidth: 200 Hz to 20 kHz, fi(ADC) = 1 kHz. 6. fripple = 1 kHz, Vripple = 0.5 V (p-p). 7. Gain of the ADC is defined as GADC = fsys/Imax (counts/A); thus digital output = Ii x GADC where: a) Digital output = the number of pulses at the digital output in counts/s and Ii = the DC input current in A. b) The maximum input current depends on RIref and on shadow registers A and C. c) The gain tolerance is the deviation from the calculated gain.
1999 Jun 17
52
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
10 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING) VDD = 3.0 to 3.6 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL PARAMETER MIN. TYP.
SAA7325
MAX.
UNIT
Subcode interface timing; d = 1 for normal operation; see Fig.32; note 1 INPUT: PIN RCK tCLKH tCLKL tr tf td(SFSY-RCK) Tcy(block) tW(SBSY) Tcy(frame) tW(SFSY) tSFSYH tSFSYL td(SFSY-SUB) td(RCK-SUB) th(RCK-SUB) Note 1. In lock-to-disc mode, the subcode timing is directly related to the disc speed factor `d'. In normal, single speed operation, d = 1. input clock HIGH time input clock LOW time input clock rise time input clock fall time delay time SFSY to RCK 2/d 2/d - - 10/d 4/d 4/d - - - 13.3/d - 136/d - - - - - - 6/d 6/d 80/d 80/d 20/d s s ns ns s ms s s s s s s s s
OUTPUTS: PINS SBSY, SFSY AND SUB (CL = 20 PF) block cycle time SBSY pulse width frame cycle time SFSY pulse width (3-wire mode only) SFSY HIGH time SFSY LOW time delay time SFSY to SUB (P data) valid delay time RCK falling to SUB hold time RCK to SUB 12.0/d - 122/d - - - - - - 14.7/d 300/d 150/d 366/d 66/d 84/d 1/d 0 0.7/d
1999 Jun 17
53
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
handbook, full pagewidth
tW(SBSY)
Tcy(block)
SBSY tSFSYH SFSY (4-wire mode) tW(SFSY) SFSY (3-wire mode) tSFSYL Tcy(frame)
SFSY 0.8 V td(SFSY-RCK) tr tf VDD - 0.8 V RCK 0.8 V td(SFSY-SUB) th(RCK-SUB) td(RCK-SUB) VDD - 0.8 V SUB 0.8 V
MGL718
Fig.32 Subcode interface timing diagram.
1999 Jun 17
54
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
11 OPERATING CHARACTERISTICS (I2S-BUS TIMING) VDD = 3.0 to 3.6 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA7325
MAX.
UNIT
I2S-bus timing (d = 1 for normal operation); see Fig.33; note 1 CLOCK OUTPUT: PIN SCLK (CL = 20 pF) Tcy output clock period sample rate = fs sample rate = 2fs sample rate = 4fs tCH clock HIGH time sample rate = fs sample rate = 2fs sample rate = 4fs tCL clock LOW time sample rate = fs sample rate = 2fs sample rate = 4fs OUTPUTS: PINS WCLK, DATA AND EF (CL = 20 pF) tsu set-up time sample rate = fs sample rate = 2fs sample rate = 4fs th hold time sample rate = fs sample rate = 2fs sample rate = 4fs Note 1. In lock-to-disk mode, the I2S-bus timing is directly related to the disc speed factor `d'. In normal operation, d = 1. 95/d 48/d 24/d 95/d 48/d 24/d - - - - - - - - - - - - ns ns ns ns ns ns - - - 166/d 83/d 42/d 166/d 83/d 42/d 472.4/d 236.2/d 118.1/d - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns
clock period Tcy t CL t CH V SCLK 0.8 V th WCLK DATA EF t su V - 0.8 V DD - 0.8 V
DD
0.8 V
MBG407
Fig.33 I2S-bus timing diagram.
1999 Jun 17
55
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
12 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING) VDD = 3.0 to 3.6 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. NORMAL MODE SYMBOL PARAMETER CONDITIONS MIN. MAX. MIN.
SAA7325
LOCK-TO-DISC MODE UNIT MAX.
Microcontroller interface timing (4-wire bus mode; writing to decoder registers 0 to F; reading Q-channel subcode and decoder status); see Figs 34 and 35; note 1 INPUTS SCL AND RAB tCL tCH tr tf tdRD tPD tdRZ input LOW time input HIGH time rise time fall time 500 500 - - - 700 - - - 480 480 2420 2420 - - - 740 - - - 480 480 ns ns ns ns
READ MODE (CL = 20 pF) delay time RAB to SDA valid propagation delay SCL to SDA delay time RAB to SDA high-impedance 50 980 50 50 4820 50 ns ns ns
WRITE MODE (CL = 20 pF) tsuD thD tsuCR tdWZ set-up time SDA to SCL hold time SCL to SDA set-up time SCL to RAB delay time SDA high-impedance to RAB note 2 -700 - 260 0 - 980 - - -700 - 1220 0 - 4820 - - ns ns ns ns
Microcontroller interface timing (4-wire bus mode; servo commands); see Figs 36 and 37; notes 3 INPUTS SCL AND SILD tL tH tr tf tdLD tPD tdLZ tsCLR thCLR input LOW time input HIGH time rise time fall time 710 710 - - - - - 480 830 - - 240 240 710 710 - - - - - 480 830 - - 240 240 ns ns ns ns
READ MODE (CL = 20 pF) delay time SILD to SDA valid propagation delay SCL to SDA delay time SILD to SDA high-impedance set-up time SCL to SILD hold time SILD to SCL 25 950 50 - - 25 950 50 - - ns ns ns ns ns
1999 Jun 17
56
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
NORMAL MODE SYMBOL PARAMETER CONDITIONS MIN. WRITE MODE (CL = 20 pF) tsD thD tsCL thCL tdPLP tdWZ Notes set-up time SDA to SCL hold time SCL to SDA set-up time SCL to SILD hold time SILD to SCL delay between two SILD pulses delay time SDA high-impedance to SILD 0 950 480 120 70 0 - - - - - - 0 950 480 120 70 0 - - - - - - MAX. MIN.
SAA7325
LOCK-TO-DISC MODE UNIT MAX.
ns ns ns ns s ns
1. In lock-to-disc mode, the maximum data rate is lower when writing to decoder registers 0 to F, and reading Q-channel subcode and decoder status. 2. Negative set-up time means that the data may change after clock transition. 3. If a 16.9344 MHz crystal is used and SELPLL = 0 then the timings are divided-by-2 until the microcontroller has written X1XX to register B.
tr
tf VDD - 0.8 V
RAB tr tf t CH VDD - 0.8 V 0.8 V t CL t PD SDA (SAA7325) high-impedance VDD - 0.8 V 0.8 V
MGL691
0.8 V
SCL
t dRD
t dRZ
Fig.34 4-wire bus microcontroller timing; read mode (Q-channel subcode and decoder status information).
1999 Jun 17
57
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
handbook, full pagewidth
tr t suCR RAB
t CH
tf V DD - 0.8 V 0.8 V
tf
t CH
tr VDD - 0.8 V
t CL
SCL 0.8 V t CL t suD SDA (microcontroller) t hD t dWZ
V DD - 0.8 V 0.8 V high-impedance
MBG405
Fig.35 4-wire bus microcontroller timing; write mode (decoder registers 0 to F).
handbook, full pagewidth
VDD - 0.8 V SILD 0.8 V t hCLR t sCLR VDD - 0.8 V SCL 0.8 V t dLD VDD - 0.8 V SDA (SAA7325) 0.8 V
MGL692
t PD
t dLZ
Fig.36 4-wire bus microcontroller timing; read mode (servo commands).
1999 Jun 17
58
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
SAA7325
handbook, full pagewidth
VDD - 0.8 V 0.8 V tsCL tH tL tdPLP VDD - 0.8 V
SILD
SCL 0.8 V thCL tsD thD VDD - 0.8 V SDA (microcontroller) 0.8 V tL tdWZ
MBG416
Fig.37 4-wire bus microcontroller timing; write mode (servo commands).
1999 Jun 17
59
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dbook, full pagewidth
VDDD2(C)
MOTO2
MOTO1
VSSD3
VSSD2
22 nF RFE 9 100 nF MECHANISM AND HF AMPLIFIER VDDA 2.2 33 F 100 nF 30 k 100 nF O2 O3 O4 O1 O5 O6 10 k 10 k 220 pF 220 pF 220 pF 220 pF 220 pF 220 pF 1 nF 1 k 47 pF 22 k
HFREF HFIN ISLICE VSSA1 VDDA1 Iref VRIN D1 D2 D3 D4 R1 R2 VSSA2 CROUT CRIN
64 1 2 3 4 5 6 7 8
63
62
61
60
59
58
57
56
55
54
53
52
51
50
CL11/4
DOBM
7
VDDD1(P)
LDON
CFLG
FO
RA
V1
V5
V4
SL
Vneg
CL16
LN
Vpos
RN
RP
WCLK
EF
VDDA2
SELPLL
TEST1
DATA
SCLK
33 pF
33 pF
100 nF
(1) For crystal oscillator see Figs 3 and 4. (2) 1.5 nF capacitors connected between pins LN and LP, and RN and RP must be placed as near to the pins as possible. This also applies to the 220 nF and 47 F capacitors connected between pins Vneg and Vpos. Power supplies and VDDD reference inputs (12VDDD)for DAC operational amplifiers must be low noise. (3) The connections to TDA1300 are shown for single Foucault mechanisms.
(2)
1.5 nF
220 nF 47 F VDDD 22 k
1.5 nF
33 F
2.2 VDDA
1/2 VDDD(2) 220 pF 11 k 22 k
1/2 VDDD(2) 22 k 22 k 220 pF 11 k
220 pF
11 k
220 pF 33 F 10 k left output
11 k 33 F 10 k right output to external DAC or ESA
TEST2
KILL
LP
1999 Jun 17
MOTOR INTERFACE LDON
13 APPLICATION INFORMATION
Philips Semiconductors
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
VDDD VDDD 2.2 100 nF
to power amplifiers
to DOBM transformer VDDD 2.2 100 nF
49 48 47 46 45 44 43 42 41
SBSY SFSY SUB RCK TEST3 STATUS SILD RAB SCL SDA RESET SCLI SDI WCLI V2/V3 VSSD1 100 nF to ESA serial data loopback to microcontroller interface VDDD 4.7 k 4.7 k to CD graphics
(TDA1300)
(3) 6 3 1 4
SAA7325
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 40 39 38 37 36 35 34 33
60
5 2
(1)
Product specification
SAA7325
MGL696
Fig.38 Typical application diagram for current mechanisms.
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dbook, full pagewidth
VDDD2(C)
7 DIN 9
VDDD1(P)
MOTO2
MOTO1
5 TZA1025 RFEQO 10 (3) 8 CMFB 100 nF 1 k 3 nF 100 nF VDDA 47 pF 22 k HFREF HFIN ISLICE VSSA1 33 F 100 nF 30 k VDDA1 Iref VRIN 1 2 3 4 5 6 7 8
DOBM
LDON
CFLG
RFFB
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
CL11/4
10 k
VSSD2
VSSD3
FO
RA
V1
V5
V4
SL
VDDA2
LN
LP
Vneg
Vpos
RN
RP
SELPLL
TEST1
CL16
DATA
WCLK
SCLK
EF
TEST2
(1) For crystal oscillator see Figs 3 and 4. (2) 1.5 nF capacitors connected between pins LN and LP, and RN and RP must be placed as near to the pins as possible. This also applies to the 220 nF and 47 F capacitors connected between pins Vneg and Vpos. Power supplies and VDDD reference inputs (12VDDD) for DAC operational amplifiers must be low noise. (3) For connections between OEIC and TZA1025, refer to TZA1025 device specification. (4) Components for LP filter and V I conversion depend on OEIC and current range set on CD10.
33 pF
33 pF
100 nF
(2)
1.5 nF
220 nF 47 F VDDD 22 k
1.5 nF
33 F
2.2 VDDA
1/2 VDDD
(2)
1/2 VDDD(2) 22 k 22 k 220 pF 11 k
220 pF
11 k
22 k
220 pF
11 k
220 pF 33 F 10 k left output
11 k 33 F 10 k right output to external DAC or ESA
KILL
1999 Jun 17
MOTOR INTERFACE PWRON
Philips Semiconductors
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
VDDD VDDD 2.2 100 nF
to power amplifiers
to DOBM transformer VDDD 2.2 100 nF
49 48 47 46 45 44 43 42 41
SBSY SFSY SUB RCK TEST3 STATUS SILD RAB SCL SDA RESET SCLI SDI WCLI V2/V3 VSSD1 100 nF to ESA serial data loopback to microcontroller interface VDDD 4.7 k 4.7 k to CD graphics
D1-D4 (3)
VCC
VCOM
2.2
D1
D1
220 pF
D2
D2 D3 D4 R1 R2 VSSA2 CROUT
SAA7325
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 40 39 38 37 36 35 34 33
220 pF
D3
220 pF
D4
220 pF
61
OEIC
(3)
S1
220 pF
S2
220 pF
LP FILTER
(4)
V
(4)
I
CRIN
(1)
Product specification
SAA7325
MGL682
Fig.39 Typical application diagram for voltage mechanisms.
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
14 PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm
SAA7325
SOT393-1
c
y X
A 48 49 33 32 ZE
e E HE wM pin 1 index 64 1 bp D HD wM ZD B vM B 16 vMA 17 bp Lp L detail X A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.00 A1 0.25 0.10 A2 2.75 2.55 A3 0.25 bp 0.45 0.30 c 0.23 0.13 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.8 HD HE L Lp 1.03 0.73 v 0.16 w 0.16 y 0.10 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
17.45 17.45 1.60 16.95 16.95
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT393-1 REFERENCES IEC JEDEC MS-022 EIAJ EUROPEAN PROJECTION
ISSUE DATE 96-05-21 97-08-04
1999 Jun 17
62
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
15 SOLDERING 15.1 Introduction to soldering surface mount packages
SAA7325
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 15.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Jun 17
63
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ not suitable suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes
SAA7325
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Jun 17
64
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7325
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1999 Jun 17
65
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
NOTES
SAA7325
1999 Jun 17
66
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc decoder with integrated DAC (CD10)
NOTES
SAA7325
1999 Jun 17
67
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 66
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/01/pp68
Date of release: 1999 Jun 17
Document order number:
9397 750 04958

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